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Area-time lower-bound techniques with applications to sorting

  • G. Bilardi
  • F. P. Preparata


Thearea-time complexity of VLSI computations is constrained by the flow and the storage of information in the two-dimensional chip. We study here the information exchanged across the boundary of the cells of asquare-tessellation of the layout. When the information exchange is due to thefunctional dependence between variables respectively input and output on opposite sides of a cell boundary, lower bounds are obtained on theAT 2 measure (which subsume bisection bounds as a special case). When information exchange is due to thestorage saturation of the tessellation cells, a new type of lower bound is obtained on theAT measure.

In the above arguments, information is essentially viewed as a fluid whose flow is uniquely constrained by the available bandwidth. However, in some computations, the flow is kept below capacity by the necessity to transform information before an output is produced. We call this mechanismcomputational friction and show that it implies lower bounds on theAT/logA measure.

Regimes corresponding to each of the three mechanisms described above can appear by varying the problem parameters, as we shall illustrate by analyzing the problem of sortingn keys each ofk bits, for whichAT 2,AT, andAT/logA bounds are derived. Each bound is interesting, since it dominates the other two in a suitable range of key lengths and computations times.

Key words

VLSI complexity Information exchange Sorting 


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Copyright information

© Springer-Verlag New York Inc. 1986

Authors and Affiliations

  • G. Bilardi
    • 1
  • F. P. Preparata
    • 2
  1. 1.Department of Computer ScienceCornell UniversityIthacaUSA
  2. 2.Coordinated Science Laboratory, Departments of Electrical Engineering and Computer ScienceUniversity of Illinois at Urbana-ChampaignUrbanaUSA

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