Optimal VLSI graph embeddings in variable aspect ratio rectangles
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We generalize earlier results in VLSI layout theory by considering variable aspect ratio embeddings for VLSI graphs. By aspect ratio we mean the ratio of the length of the longer side to the length of the shorter side of the bounding rectangle of the embedding. Our results are based on separators and bifurcators. We obtain embeddings with existentially optimal area and any desired aspect ratio. Additionally, we can obtain either bounded capacitive delay or existentially optimal minimax edge length in the embeddings; both of these features reduce delays in the circuit.
A special feature of our results on minimax edge length is that they unify earlier separator- and bifurcator-based results for square embeddings, and also provide a simplified lower bound proof.
Key wordsVLSI layout Graph embedding Variable aspect ratio rectangles
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