Abstract
Circuits, especially logic circuits, are highly concurrent structures: signals flow along many parallel paths at once. This “native” concurrency, a function of both circuit size and topology, can be exploited in simulating these circuits on parallel machines. Simulation efficiency is affected by machine, language, and simulator implementation parameters like cycle speed, parallelism overhead, and partitioning of the circuit within the simulator, as well as by the amount of native concurrency. The experimental logic simulatorconsim, written in Multilisp and implemented on a 34 element shared-memory multiprocessor, was used to investigate these issues.
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Bradley, E., Halstead, R.H. Simulating logic circuits: A multiprocessor application. Int J Parallel Prog 16, 305–338 (1987). https://doi.org/10.1007/BF01407939
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DOI: https://doi.org/10.1007/BF01407939