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Cache coherence requirements for interprocess rendezvous

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Abstract

Multiprocessors in which a shared bus is used by the processor to communicate with common memory are an emerging class of machines where there is a need to support parallel programming languages. A language construct that is found in a number of parallel programming languages to support synchronization and communication in the interprocess rendezvous. Shared-bus multiprocessor require a protocol to keep the date in their caches coherent. There are two major categories of these protocols: invalidation and write-boadcast. This paper examines the requirements for cache coherence protocols to support efficient interprocessor rendezvous. The approach taken is to examine the memory referencing patterns to the run-time data structures during rendezvous execution. The appropriate coherence protocol is shown to be a function of the processor scheduling strategy used by the run-time system at synchronzation points during the rendezvous. When processes migrate freely as a result of the scheduling strategy, invalidation protocols are found to be more efficient. When migration is restricted by the scheduler, write-broadcast protocols are more efficient.

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  1. Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, The University of Michigan, 48109-2122, Ann Arbor, Michigan

    Trevor N. Mudge

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  1. Russell M. Clapp
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  2. Trevor N. Mudge
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  3. Donald C. Winsor
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Clapp, R.M., Mudge, T.N. & Winsor, D.C. Cache coherence requirements for interprocess rendezvous. Int J Parallel Prog 19, 31–51 (1990). https://doi.org/10.1007/BF01407863

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  • DOI: https://doi.org/10.1007/BF01407863

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