Abstract
This paper describes a verification technique that 1) enables a designer to verify properties of a partial design where some parts have not yet been completed, 2) yields a number of verification conditions growing linearly with the size of the design description. The technique was developed as part of work aimed at providing high-level tools for specification, verification, analysis, and synthesis of circuit descriptions written in a design language calledSynchronized Transitions [18]. The verification is supported by the mechanical theorem proverlp [5, 10].
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References
R.E. Bryant, “Can a Simulator Verify a Circuit?”Formal Aspects of VLSI Design, North-Holland, 1985, pp. 125–136.
K. Mani Chandy and J. Misra,Parallel Program Design: A Foundation, Addison-Wesley, 1988.
R.W. Floyd, “Assigning meanings to programs,” in J.T. Schwartz, editor,Proceedings of the Symposium in Applied Mathematics, American Mathematical Society, 1967, Vol. 19, pp. 19–32.
Michael P. Fourman and Robert L. Harris, “Lambda—logic and mathematics behind design automation,” inProceedings of the 26th ACM/IEEE Design Automation Conference, ACM, 1989.
Stephen J. Garland and John V. Guttag, “A guide to LP, the Larch Prover,” Technical Report 82, Digital SRC, 1991.
Stephen J. Garland, John V. Guttag, and Jørgen Staunstrup, “Verification of VLSI circuits using LP,” inThe Fusion of Hardware Design and Verification, IFIP WG. 10.2, North Holland, 1988, pp. 329–346.
Mike Gordon, “Why higher-order logic is a good formalism for specifying and verifying hardware,” inFormal Aspects of VLSI Design, North-Holland, 1985, pp. 153–177.
Mike Gordon, “HOL A Proof Generating System for Higher-Order Logic,”VLSI Specification, Verification and Synthesis, 1987.
Aarti Gupta, “Formal hardware verification methods: A survey,”Formal Methods in Systems Design, 1(2/3):151–238, October 1992.
John V. Guttag, James J. Horning, S.J. Garland, K.D. Jones, A. Modet, and J.M. Wing,Larch: Languages and Tools for Formal Specification, Springer-Verlag Texts and Monographs in Computer Science, 1993.
Warren A. Hunt, “FM8501: A verified microprocessor,” inFrom HDL Descriptions to Guaranteed Correct Circuit Designs, North-Holland, 1986, pp. 85–114.
Jeffrey J. Joyce, “Generic specification of digital hardware,” inDesigning Correct Circuits, Oxford 1990, Springer-Verlag, 1991, pp. 68–91.
J.C. Madre and J.P. Billon, “Proving circuit correctness using formal comparison between expected and extracted behavior,”Proceedings of the 25th ACM/IEEE Design Automation Conference, ACM, 1988, pp. 205–210.
Niels Maretti, “Mechanized verification of refinement,” inProceedings from TPCD'94, Springer Lecture Notes, Vol. 901, pp. 185–202.
Kenneth L. McMillan,Symbolic Model Checking, Kluwer Academic Publishers, 1993.
Niels Mellergaard, “Mechanized Design Verification,” PhD thesis, Department of Computer Science, Technical University of Denmark, 1994.
David E. Muller, “Asynchronous logics and application to information processing,” in H. Aiken and W.F. Main, editors,Proc. Symp. on Application of Switching Theory in Space Technology, Stanford University Press, 1963, pp. 289–397.
Jørgen Staunstrup,A Formal Approach to Hardware Design, Kluwer Academic Publishers, 1994.
John P. Van Tassel, “A formalisation of the VHDL simulation cycle,” in L.J.M. Claesen and M.J.C. Gordon, editors,Higher Order Logic Theorem Proving and its Applications, Vol. IFIP Transactions A-20, Elsevier, 1993, pp. 359–374.
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Staunstrup, J., Mellergaard, N. Localized verification of modular designs. Form Method Syst Des 6, 295–320 (1995). https://doi.org/10.1007/BF01384501
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DOI: https://doi.org/10.1007/BF01384501