Skip to main content
SpringerLink
Log in

Gordon's computer: A hardware verification case study in OBJ3

  • Published:
Formal Methods in System Design Aims and scope Submit manuscript

Abstract

The use of the algebraic specification language OBJ3 [26] in hardware verification has been demonstrated on a number of small examples [62, 20, 63] and some large but regular structures [12, 11]. In this paper, we show that the approach can also be used for specifying and verifying large, irregular structures. We specify and partially verify Gordon's computer, a simple microprocessor. We believe that this is the largest hardware verification case study undertaken with OBJ3 so far.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Bainbridge, S., Camilleri, A., and Fleming, R., Theorem Proving as an Industrial Tool for System Level Design. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 253–276. North-Holland, 1992.

  2. Barrow, H.G., VERIFY. A Program for Proving Correctness of digital Hardware Designs.Artificial Intelligence, 24(1–3), December 1984.

  3. Bickford, M. and Srivas, M., Verification of a Fault-Tolerant Property of a Multiprocessor System: A Case Study in Theorem Prover-Based Verification. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 225–252. North-Holland, 1992.

  4. Brock, B.C., Hunt, Jr., W.A., and Young, W.D., Introduction to a Formally Defined Hardware Description Language. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 3–35. North-Holland, 1992.

  5. Burrows, M., Abadi, M., and Needham, R., A logic of Authentication. Technical Report 39, DEC Systems Research Center, February 1989.

  6. Burstall, R. and Goguen, J.A., Algebras, Theories and Freeness: An Introduction for Computer Scientists. In M. Wirsing and G. Schmidt, editors,Theoretical Foundations of Programming Methodology, pages 329–350. Reidel, 1982.

  7. Chandrasekhar, M.S., Privitera, J.P., and Conradt, K.W., Application of Term Rewriting Techniques to Hardware Design Verification. InProcs, 24th Design Automation Conference, Miami, Florida, June 1987.

  8. Cohn, A.J., Correctness Properties of the Viper Block Model: the Second Level. In P.A. Subramanyan, editor,Procs of 2nd Banff Workshop on Hardware Verification, Banff, Canada, June 1988. Springer-Verlag.

  9. Cohn, A.J., A Proof of Correctness of the Viper Microprocessor: The First Level. InVLSI Specification, Verification and Synthesis, Boston, 1988. Kluwer Academic Publishers.

  10. Coleman, D. et al., An Introduction to the Axis Specification Language. Technical Report HPL-ISC-TR-88-031, Hewlett-Packard Laboratories, Filton Rd, Stoke Gifford, Bristol BS12 6QZ, UK, September 1988.

  11. Eker, S.M., Verification of a Line Drawing Architecture Using OBJ3. InProceedings of Workshop on Formal Methods in Computer Graphics, Marina di Carrara, Italy, June 1991.

  12. Eker, S.M., Stavridou, V., and Tucker, J.V., Verification of Synchronous Concurrent Algorithms Using OBJ3: a Case Study of the Pixel Planes Architecture. In G. Jones and M. Sheeran, editors,Designing Correct Circuits, pages 231–252. Springer-Verlag, 1991.

  13. Gallimore, R.M., Coleman, D., and Stavridou, V., UMIST OBJ: A Language for Executable Program Specifications.Computer Journal, 32(5):413–421, October 1989.

    Google Scholar 

  14. Garland, S.J. and Guttag, J.V., Why Induct Inductionlessly When You Could Induct Inductively? Draft paper, April 1987.

  15. Garland, S.J. and Guttag, J.V., An Overview of LP, the Larch Prover. InProcs of 3rd International Conference on Rewriting Techniques and Applications, LNCS 355, pages 137–151, Chapel Hill, N.C., 1989. Springer-Verlag.

  16. Garland, S.J., Guttag, J.V., and Staunstrup, J., Verification of VLSI Circuits Using LP. InProcs of Workshop on the Fusion of Hardware Design and Verification. IFIP WG 10. 2, North-Holland, 1988.

  17. Geser, A., A Specification of the INTEL 8085 Microprocessor: A Case Study. Technical Report MIP-8608, Faculty for Mathematics and Informatics, University of Passau, May 1986.

  18. Geser, A. and Hussmann, H., Experiences with the RAP System—a Specification Interpreter Combining Term Rewriting and Resolution. InProcs of ESOP Conference, 1986.

  19. Goguen, J.A., How to Prove Algebraic Inductive Hypotheses Without Induction, with Applications to the Correctness of Data Type Implementation. In W. Bibel and R. Kowalski, editors,Procs of 5th Conference on Automated Deduction, LNCS 87, pages 356–373, Les Arc, July 1980. Springer-Verlag.

  20. Goguen, J.A., OBJ as a Theorem Prover with Applications to Hardware Verification. InProcs of 2nd Banff Workshop on Hardware Verification, Banff, Canada, June 1988.

  21. Goguen, J.A., Kirchner, C., Meseguer, J., and Winkler, T., OBJ as a Language for Concurrent Programming. In S. Kartashev and S. Kartashev, editors,Procs of 2nd International Supercomputing Conference, Vol 1, pages 195–198, St. Petersburg, Florida, 1987. International Supercomputing Institute Inc.

  22. Goguen, J.A. and Meseguer, J., Rapid Prototyping in the OBJ Executable Specification Language.Sofware Engineering Notes, 7(5):75–84, December 1982.

    Google Scholar 

  23. Goguen, J.A. and Meseguer, J., Order Sorted Algebra I: Equational Deduction for Multiple Inheritance, Overloading, Exceptions and Partial Operations. Technical Report SRI-CSL-89-19, Computer Science Laboratory, SRI International, July 1989.

  24. Goguen, J.A., Stevens, A., Hilberdink, H., and Hobley, K.M., 2OBJ: a Metalogical Framework Theorem Prover Based on Equational Logic. In C.A.R. Hoare and M.J.C. Gordon, editors,Mechanised Reasoning and Hardware Design, Prentice Hall International Series in Computer Science, pages 69–86. Prentice Hall, 1992.

  25. Goguen, J.A. and Tardo, J., An Introduction to OBJ: A Language for Writing and Testing Software Specifications. In M. Zelkcwitz, editor,Specification of Reliable Software, pages 170–189. IEEE Press, 1979.

  26. Goguen, J.A. and Winkler, T., Introducing OBJ3. Technical Report SRI-CSL-88-9, Computer Science Laboratory, SRI International, Menlo Park, CA 94025, August 1988.

  27. Gordon, M.J.C., LCF-LSM: A System for Specifying and Verifying Hardware. Technical Report 41 University of Cambridge Computer Laboratory, Corn Exchange Street, Cambridge CB2 3QK, UK, 1983.

    Google Scholar 

  28. Gordon, M.J.C., Proving a Computer Correct with the LCF-LSM Hardware Verification System. Technical Report 42, University of Cambridge Computer Laboratory, Corn Exchange Street, Cambridge CB2, 3QG, UK, 1983.

    Google Scholar 

  29. Gordon, M.J.C., HOL: A Machine Oriented Formulation of Higher Order Logic. Technical Report 68, University of Cambridge Computer Laboratory, Corn Exchange Street, Cambridge CB2 3QG, UK, July 1985.

    Google Scholar 

  30. Graham, B.T.,The SECD Microprocessor—a Verification Case Study. Kluwer Academic Publishers, 1992.

  31. Guttag, J.V. and Horning, J.J., Report on the Larch Shared Language.Science of Computer Programming, 6(2):103–157, March 1986.

    Google Scholar 

  32. Herbert, J.M.J., Incremental Design and Formal Verification of Microcoded Microprocessors. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 157–174. North-Holland, 1992.

  33. Hsiang, J.,Refutational Theorem Proving using Term Rewriting Systems. PhD thesis, University of Illinois at Champaign-Urbana, 1981.

  34. Hunt, Jr., W.A.,FM8501: A Verified Microprocessor. PhD thesis, University of Texas at Austin, Austin, Texas 78712, December 1985.

    Google Scholar 

  35. Hunt, Jr., W.A., Microprocessor Design Verification.Journal of Automated Reasoning, 5:429–460, 1989.

    Google Scholar 

  36. Hunt, Jr., W.A, and Brock, B.C., A Formal HDL and its Use in the FM9001 Verification. In C.A.R. Hoare and M.J.C. Gordon, editors,Mechanised Reasoning and Hardware Design, Prentice Hall International Series in Computer Science, pages 35–47. Prentice Hall, 1992.

  37. Hussmann, H., Unification in Conditional-Equational Theories. InProcs of EURO-CAL 85, LNCS 204, pages 543–553. Springer-Verlag, 1985.

  38. Joyce, J., Formal Verification and Implementation of a Microprocessor. InVLSI Specification, Verification and Synthesis, Boston, 1988. Kluwer Academic Publishers.

  39. Joyce, J., Birtwistle, G., and Gordon, M.J.C., Proving a Computer Correct in Higher Order Logic. Technical Report 100, University of Cambridge Computer Laboratory, Corn Exchange Street, Cambridge CB2 3QG, UK, December 1986.

    Google Scholar 

  40. Joyce, J., Rajan, S., and Zhu, Z., A Virtuoso Performance Becomes Routine Practice: A Re-verification of the Viper Microprocessor Using a Combination of Interactive Theorem-proving and BDD-based Symbolic Trajectory Evaluation. InProceedings of IMA Conference on the Mathematics of Dependable Systems. Oxford University Press, 1993. to appear.

  41. Kapur, D. and Musser, D.R., Tecton: a Framework for specifying and Verifying Generic System Components. Presented at the IFIP TC10/WG10.2 Conference on Theorem Provers in Circuit Design, Nijmegen, The Netherlands (available from D.R. Musser, Rensselaer Polytechnic Institute, Troy, New York 12180), June 1992.

  42. Kapur, D., Musser, D.R., and Nie, X., An Overview of the Tecton Proof System. InProcs of a Workshop on Formal Methods in Databases and Software Engineering, Concordia University, Montreal, May 1992.

  43. Kapur, D. and Narendran, P., An Equational Approach to Theorem Proving in First Order Predicate Calculus. Unpublished manuscript, April 1984.

  44. Kapur, D., Sivakumar, G., and Zhang, H., RRL: A Rewrite Rule Laboratory. InProcs of 8th Conference on Automated Deduction, Oxford, UK, 1986.

  45. Lamport, L. and Schneider, F.B., The “Hoare Logic” of CSP and All That.ACM Trans on Programming Languages, 6(2), April 1984.

  46. Levy, B., Filippenko, I., Marcus, L., and Menas, T., Using the State Delta Verification System (SDVS) for Hardware Verification. In V. Stavridou, T.F. Melham and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 337–360. North-Holland, 1992.

  47. May, D., Barrett, G., and Shepherd, D., Designing Chips That Work. In C.A.R. Hoare and M.J.C. Gordon, editors,Mechanised Reasoning and Hardware Design, Prentice Hall International Series in Computer Science, pages 3–18. Prentice Hall, 1992.

  48. May, D. and Shepherd, D.E., Formal Verification of IMS T800 Microprocessor. InProcs of Electronic Design Automation, pages 605–615, London, UK, September 1987.

  49. Meseguer, J. and Goguen, J.A., Initiality, Induction and Computability. In M. Nivat and J. Reynolds, editors,Algebraic Methods in Semantics, pages 459–541. Cambridge University Press, 1985.

  50. Musser, D.R. and Cyrluk, D.A.,Affirm-85 Reference Manual. General Electric Corporate Research and Development Center, Schenectady, NY 12301, August 1985.

  51. Musser, D.R., Narendran, P., and Premerlani, W.J., BIDS: A Method for Specifying and Verifying Bidirectional Hardware Devices. InProc. of Hardware Verification Workshop, Calgary, Canada, January 1987.

  52. Narendran, P. and Stillman., J., Hardware Verification in the Interactive VHDL Workstation. G.E. Corporate Research and Development Center, Schenectady, NY 12345, USA, 1986.

    Google Scholar 

  53. Roscoe, A.W., Occam in the Specification and Verification of Microprocessors. In C.A.R. Hoare and M.J.C. Gordon, editors,Mechanised Reasoning and Hardware Design, Prentice Hall International Series in Computer Science, pages 137–151. Prentice Hall, 1992.

  54. Sampaio, A., A Comparative Study of Theorem Provers: Proving Correctness of Compiling Specifications. Master's thesis, Programming Research Group, Oxford University Computing Laboratory, 8–11 Keble Road, Oxford OX1 3QD, UK, September 1990.

    Google Scholar 

  55. Sampaio, A.B.C. and Parsaye-Ghomi, K., The Formal Specification and Testing of Expanded Hardware Building Blocks. InProcs. of Computer Science Conference, Rolla, MO, 1981. ACM.

  56. Saxe, J.B., Garland, S.J., Guttag, J.V., and Horning, J.J., Using Transformations and Verification in Circuit Design. Technical Report 78, DEC Systems Research Centre, 130 Lytton Avenue, Palo Alto, CA 94301, September 1991.

    Google Scholar 

  57. Shankar, N., Owre, S., and Rushby, J.M.,User Guide for the PVS Specification and Verification System. 333 Ravenswood Ave, Menlo Park, CA 94025, March, 1993.

  58. Shepherd, D.E., Verified Microcode Design.Microprocessors and Microsystems, 14(10):623–630, December 1990.

    Google Scholar 

  59. Smolka, G., Nutt, W., Goguen, J.A., and Meseguer, J., Order-Sorted Equational Computation. In H. Ait-Kaci and M. Nivat, editors,Resolution of Equations in Algebraic Structures, pages 299–367, New York, 1989. Academic Press.

    Google Scholar 

  60. Staunstrup, J., Garland, S.J., and Guttag, J.V., Mechanized Verification of Circuit Descriptions Using the Larch Prover. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 277–300. North-Holland, 1992.

  61. Staunstrup, J. and Greenstreet, M., Synchronised Transitions. In J. Staunstrup, editor,Formal Methods for VLSI Design, pages 71–128. North-Holland, 1990.

  62. Stavridou, V., Specifying in OBJ, Verifying in REVE and Some Ideas About Time. Technical Report CSDTR-605, Department of Computer Science, RNBNC, University of London, Egham Hill, Egham, Surrey TW20 OEX, UK, October 1988.

    Google Scholar 

  63. Stavridou, V., Specification and Verification of Finite State Machines. Technical Report CSD-TR-636, Department of Computer Science, RHBNC, University of London, Egham Hill, Egham, Surrey TW20 OEX, UK, November 1990.

    Google Scholar 

  64. Stavridou, V.,Formal Methods in Circuit Design, volume 37 ofCambridge Tracts in Theoretical Computer Science. Cambridge University Press, Cambridge, UK, 1993.

    Google Scholar 

  65. Stavridou, V., Goguen, J.A., Eker, S.M., and Aloneftis, S.N., FUNNEL: a CHDL with Formal Semantics. InProceedings of IFIP TC 10/WG 10.2 Advanced Research Workshop on Correct Hardware Design Methodologies, pages 117–144, Turin, Italy, June 1991. North-Holland.

  66. Stavridou, V., Goguen, J.A., Stevens, A., Eker, S.M., Aloneftis, S.N., and Hobley, K.M., FUNNEL and 20BJ: Towards an Integrated Hardware Design Environment. In V. Stavridou, T.F. Melham, and R.T. Boute, editors,Theorem Provers in Circuit Design, volume A-10 ofIFIP Transactions, pages 197–224. North-Holland, 1992.

  67. Weise, D.W.,Formal Multilevel Hierarchical Verification of Synchronous MOS VLSI Circuits. PhD thesis, MIT, August 1986.

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, Royal Holloway, University of London, Egham Hill, TW20 OEX, Egham, Surrey, UK

    Victoria Stavridou

Authors
  1. Victoria Stavridou
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Stavridou, V. Gordon's computer: A hardware verification case study in OBJ3. Form Method Syst Des 4, 265–310 (1994). https://doi.org/10.1007/BF01384049

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01384049

Keywords

Search

Navigation