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An exercise in the automatic verification of asynchronous designs

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Abstract

This paper illustrates the practical application of an automatic formal verification technique to circuit designs of realistic complexity. The Circal System is presented and a number of asynchronous hardware modules are described and formally verified using it. Asynchronous logic is generally considered hard to design and analyse, and this serves as an appropriate demonstration of the features of a formal description and verification system.

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Authors and Affiliations

  1. Department of Mathematics and Computing Science, Eindhoven University of Technology, P.O. Box 513, 5600 MB, Eindhoven, The Netherlands

    Andrew Bailey

  2. Requirement Engineering Ltd, 12 Viewpark Terrace, Edinburgh, UK

    George A. Mccaskill

  3. School of Computer and Information Science, University of South Australia, The Levels, 5095, Adelaide, S.A., Australia

    George J. Milne

Authors
  1. Andrew Bailey
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  2. George A. Mccaskill
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  3. George J. Milne
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Bailey, A., Mccaskill, G.A. & Milne, G.J. An exercise in the automatic verification of asynchronous designs. Form Method Syst Des 4, 213–242 (1994). https://doi.org/10.1007/BF01384047

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  • DOI: https://doi.org/10.1007/BF01384047

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