Formal Methods in System Design

, Volume 4, Issue 1, pp 33–75 | Cite as

Analysis and identification of speed-independent circuits on an event model

  • M. Kishinevsky
  • A. Kondratyev
  • A. Taubin
  • V. Varshavsky


The object of this article is the analysis of asynchronous circuits for speed independence or delay insensitivity. The circuits are specified as a netlist of logic functions describing the components. The analysis is based on a derivation of an event specification of the circuit behavior in a form of a signal graph. Signal graphs can be viewed either as a formalization of timing diagrams, or as a signal interpreted version of marked graphs (a subclass of Petri nets). The main advantage of this method is that a state explosion is avoided. A restoration of an event specification of a circuit also helps to solve the behavior identification problem, i.e., to compare the obtained specification with the desired specification. We illustrate the method by means of some examples.


speed-independent circuits delay-insensitive circuits event models signal graph analysis identification verification 


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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • M. Kishinevsky
    • 1
    • 2
  • A. Kondratyev
    • 1
    • 3
  • A. Taubin
    • 1
    • 3
  • V. Varshavsky
    • 1
    • 3
  1. 1.R&D Coop TRASSASt. PetersburgRussia
  2. 2.Technical University of DenmarkLyngbyDenmark
  3. 3.The University of AizuJapan

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