The Journal of Supercomputing

, Volume 8, Issue 2, pp 163–185

A Cache coherence protocol for MIN-based multiprocessors

  • Mazin S. Yousif
  • Chita R. Das
  • Matthew J. Thazhuthaveetil

DOI: 10.1007/BF01204660

Cite this article as:
Yousif, M.S., Das, C.R. & Thazhuthaveetil, M.J. J Supercomput (1994) 8: 163. doi:10.1007/BF01204660


In this paper we present a cache coherence protocol formultistage interconnection network (MIN)-based multiprocessors with two distinct private caches:privateblocks caches (PCache) containing blocks private to a process andshared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducingTransient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.


Caches cache coherence mean value analysis multiprocessor system multistage interconnection network split cache 

Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • Mazin S. Yousif
    • 1
  • Chita R. Das
    • 2
  • Matthew J. Thazhuthaveetil
    • 3
  1. 1.Department of Computer ScienceLouisiana Tech UniversityRuston
  2. 2.Department of Computer Science & EngineeringThe Pennsylvania State UniversityUniversity Park
  3. 3.Supercomputer Education and Research Center and Department of Computer Science and AutomationIndian Institute of ScienceBangaloreIndia

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