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Single-layer cylindrical compaction

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Abstract

In VLSI compaction, an array composed of a single cell warrants special consideration. Standard methods of compaction [MS] result in either nonuniform cell layouts or unnecessarily large cell spacing. These inadequacies would be lessened were the array compacted instead by compacting a single instance of the cell against itself: in essence, the cell would be compacted on a torus. Equivalently, the problem becomes that of compacting a layout to fit into a minimal area shape 4-tiling the plane.

Only the one-dimensional version of the problem has been addressed: that equivalent to compaction on a cylinder. Unfortunately, the efficient longest-path approach to one-dimensional compaction is not directly applicable since there is no origin to compact against. Eichenberger and Horowitz solve the problem in polynomial time by using a min-cost flow approach to assign positions to the nodes of a constraint network embedded on a cylinder [EH]. Mehlhorn and Rülling found an iterative approach running in timeO(n 2 logn) when restricted to networks abstracted from layouts having any fixed number of layers [MR]. In this paper the longest-path approach is adapted to solve the same cylindrical compaction problem on planar networks—those abstracted from single-layer layouts—in justO(n logn) time.

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References

  1. D. Boyer. Symbolic layout compaction review. InProceedings of the 15 th Design Automation Conference, pp. 383–389, 1988.

  2. R. Cole and A. Siegel. River routing every which way, but loose. InProceedings of the 25th Symposium on the Foundation of Computer Science, pp. 65–73, October 1984.

  3. P. Eichenberger and M. Horowitz. Toroidal compaction of symbolic layouts for regular structures. InProceedings of the International Conference on Computer Aided Design, pp. 142–145, November 1987.

  4. Z. Galil and E. Tardos. AnO(n 2(m+n logn) logn)min-cost flow algorithm. InProceedings of the 27th Symposium on Foundations of Computer Science, pp. 1–9, 1986.

  5. G. Kedem and H. Watanabe. Graph-optimization techniques for IC layout and compaction. InProceedings of the 20th Design Automation Conference, pp. 113–120, June 1983.

  6. M. Kruckenberg. CMPT: a tile compactor for Magic files. Master's thesis, University of California, Santa Cruz, CA, June 1990.

    Google Scholar 

  7. C. E. Leiserson and F. Miller Maley. Algorithms for routing and testing routability of planar VLSI layouts. InProceedings of the 17th Symposium on the Theory of Computing, pp. 69–78, May 1985.

  8. T. Lengauer. The complexity of compacting hierarchically specified layouts of integrated circuits. InProceedings of the 23rd Symposium on Foundations of Computer Science, pp. 358–368, November 1982.

  9. Y. Z. Liao and C. K. Wong. An algorithm to compact a VLSI symbolic layout with mixed constraints.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2(2):62–69, April 1983.

    Google Scholar 

  10. K. Mehlhorn and S. Näher. A faster compaction algorithm with automatic jog insertion. InProceedings of the Advanced Research in VLSI Conference, pp. 297–314, 1988.

  11. F. Miller Maley. Compaction with automatic jog insertion. InProceedings of the Chapel Hill Conference on VLSI, pp. 261–283, May 1985.

  12. F. Miller Maley. Toward a mathematical theory of single-layer wire routing. InProceedings of the Advanced Research in VLSI Conference, pp. 277–296, 1988.

  13. K. Mehlhorn and W. Rülling. Compaction on the torus.IEEE Transaction on Computer-Aided Design,9(4):389–397, April 1990.

    Google Scholar 

  14. D. Mlynski and C.-H. Sung. Layout compaction. In T. Ohtsuki, editor,Layout Design and Verification, Chapter 6. Elsevier (North Holland), Amsterdam, 1986.

    Google Scholar 

  15. M. Schlag, Y. Z. Liao, and C. K. Wong. An algorithm for optimal two dimensional compaction of VLSI layouts.integration, the VLSI Journal 1(2&3):179–209, October 1983.

    Google Scholar 

  16. M. Schlag, F. Luccio, P. Maestrini, D. T. Lee, and C. K. Wong. A visibility problem in VLSI layout compaction. In F. P. Preparata, editor,Advances in Computing Research: VLSI Theory, vol. 2, pp. 259–282. JAI Press, Greenwich, 1984.

    Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science and Engineering FR-35, University of Washington, 98195, Seattle, WA, USA

    Richard Anderson & Simon Kahan

  2. Computer Engineering Board of Studies, University of California, 225 Applied Sciences, 95064, Santa Cruz, CA, USA

    Martine Schlag

Authors
  1. Richard Anderson
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  2. Simon Kahan
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  3. Martine Schlag
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Additional information

Communicated by Kurt Mehlhorn.

This research was supported by NSF Presidential Young Investigator Grant MIP-8657693.

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Anderson, R., Kahan, S. & Schlag, M. Single-layer cylindrical compaction. Algorithmica 9, 293–312 (1993). https://doi.org/10.1007/BF01190901

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  • DOI: https://doi.org/10.1007/BF01190901

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