Skip to main content
SpringerLink
Log in

High-level synthesis: current status and future prospects

  • Published:
Circuits, Systems and Signal Processing Aims and scope Submit manuscript

Abstract

High-level synthesis is becoming increasingly important in the area of VLSI CAD. During the last decade, much research has been carried out in this area and some results have been achieved. This paper presents a survey on the state-of-the-art of current high-level synthesis research and applications. Besides basic knowledge, a comprehensive overview has been conducted among the various theories, methods, algorithms, and applications of the existing systems. Their advantages, limitations, and feasibilities are also described. Finally, some points on current status and future directions of high-level synthesis are addressed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. V. D. Agrawal and K. T. Cheng, Test function specification in synthesis,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 235–240, 1990.

  2. T. Aoyagi et al., Temporal programming language Tokio,Logic Programming Conf. '85, Berlin: Springer-Verlag, pp. 128–137, 1985.

    Google Scholar 

  3. M. Balakrishnan et al., Allocation of multi-port memories in data path synthesis,IEEE Trans. on CAD, Vol. 7, pp. 536–540, April 1988.

    Google Scholar 

  4. M. R. Barbacci,Automated Exploration of the Design Space for Register-Transfer (RT) Systems, Ph.D. thesis, Carnegie-Mellon University, Pittsburgh, PA, 1973.

    Google Scholar 

  5. M. R. Barbacci, Instruction set processor specifications (ISPS): The notation and its applications,IEEE Trans. on Comput., Vol. C-30, No. 1, pp. 24–40, 1981.

    Google Scholar 

  6. M. Bayoumi et al., Sphinx: A high level synthesis system for DSP design,IEEE Int'l Symposium on Circuits and Systems, San Diego, CA, pp. 172–175, May 1992.

  7. Benchmarks for the Fourth International Workshop on High-Level Synthesis, 1989.

  8. R. A. Bergamaschi et al., Data path synthesis using path analysis,Proc. 28th ACM/IEEE Design Automation Conf., June 1991.

  9. J. Bhasker and H. Lee, An optimizer for hardware synthesis,IEEE Design & Test of Computers, pp. 20–36, Oct. 1990.

  10. G. Borriello and W. Detjens, High-level synthesis: Current status and future directions,Proc. of the 25th ACM/IEEE Design Automation Conf., pp. 477–482, June 1988.

  11. G. Borriello et al., Private communication: high-level synthesis workshop, presented at the 25th Design Automation Conf., June 1988.

  12. R. Brayton, Algorithms for multi-level synthesis and optimization,Proc. NATO ASI, L'Aquila, Italy, Martinus Nijhoff, 1986.

    Google Scholar 

  13. R. K. Brayton et al., The Yorktown silicon compiler, inSilicon Compilation, D. D. Gajski, ed., Reading, MA: Addison-Wesley, pp. 204–311, 1988.

    Google Scholar 

  14. F. Brewer and D. Gajski, Chippe: a system for constraint driven behavioral synthesis,IEEE Trans. on CAD, Vol. 9, No. 7, pp. 681–694, July 1990.

    Google Scholar 

  15. R. Camposano and L. Treff, STRUDEL-Eine Sprache zur Spezifikation der Struktur Digitaler Schaltungen, Rep. 7/84, Fakultäet für Informatik, Univ. Karlsruhe, 1984.

    Google Scholar 

  16. R. Camposano and W. Rosenstiel, A design environment for the synthesis of integrated circuits,11th Symp. Microprocessing and Microprogramming EUROMICRO '85, Brussels, Belgium, pp. 211–215, Sept. 1985.

  17. R. Camposano and R. K. Brayton, Partitioning before logic synthesis,Proc. of ICCAD-87, pp. 324–326, 1987.

  18. R. Camposano, Design process model in the Yorktown silicon compiler,Proc. of the 25th ACM/IEEE Design Automation Conf., pp. 489–494, June 1988.

  19. R. Camposano, Structural Synthesis in the Yorktown Silicon Compiler, inVLSI '87, VLSI Design of Digital Systems, C. H. Sequin, ed., pp. 61–72, Vancouver: North-Holland, 1988.

    Google Scholar 

  20. R. Camposano and W. Rosenstiel, Synthesizing circuits from behavioral descriptions,IEEE Trans. on CAD, Vol. 8, No. 2, pp. 171–180, June 1989.

    Google Scholar 

  21. R. Camposano and R. M. Tabet, Design representation for the synthesis of behavioral VHDL models,Proc. of the 9th Int'l Conf. on CHDL, New York: Elsevier/North-Holland, June 1989.

    Google Scholar 

  22. R. Camposano, Behavior-preserving transformations for high-level synthesis,Proc. Workshop on Hardware Specification, Verification, and Synthesis: Mathematical Aspects, New York: Springer-Verlag, 1989.

    Google Scholar 

  23. R. Camposano, From behavior to structure: high-level synthesis,IEEE Design & Test of Computers, pp. 8–18, Oct. 1990.

  24. R. Camposano and R. A. Bergamaschi, Synthesis using path-based scheduling: Algorithms and exercises,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 450–455,1990.

  25. R. Camposano and R. A. Bergamaschi, Redesign Using State Splitting,Proc. of the European Design Automation Conf. '90, pp. 157–161, Glasgow, Scotland, March 1990.

  26. R. Camposano, Path-based scheduling for synthesis,IEEE Trans. on CAD, Vol. 10, No. 1, pp. 85–93, Jan. 1991.

    Google Scholar 

  27. R. Camposano et al., The IBM High-Level Synthesis System,High-Level VLSI Synthesis, R. Camposano and Wayne Wolf, eds., Norwell, MA: Kluwer, 1991.

    Google Scholar 

  28. R. Camposano and W. Wolf,High-level VLSI Synthesis, Norwell, MA: Kluwer Academic Publishers, 1991.

    Google Scholar 

  29. R. Camposano et al., The IBM high-level synthesis system, inHigh-Level VLSI Synthesis, R. Camposano and W. Wolf, eds., pp. 79–104, Norwell, MA: Kluwer Academic Publishers, 1991.

    Google Scholar 

  30. A. E. Casavant et al., A synthesis environment for designing DSP systems,IEEE Design & Test of Computers, pp. 35–45, April 1989.

  31. F. Catthoor, Architectural design strategies for complex DSP systems in an automated synthesis environment, Ph.D. dissertation, Dept. of Electrical Engineering, Katholieke Universiteit Leuven, Belgium (IMEC), May 1987.

    Google Scholar 

  32. Y. Y. Chen et al., MULTIPAR behavioral partition for synthesizing application-specific multiprocessor architectures,Proc. European Design Automation Conf. 92, pp. 14–18, 1992.

  33. H. D. Cheng and L. Wang, Energy-function approach to high-level synthesis scheduling,IEEE Int'l Symposium on Circuits and Systems, San Diego, CA, pp. 2961–2964, May 1992.

  34. C. M. Chu et al., HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications,Proc. of ICCAD '89, pp. 432–435, Oct. 1990.

  35. M. J. Chung and S. Kim, An objected-oriented VHDL design environment,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 431–436, 1990.

  36. R. Cloutier and D. Thomas, The Combination of Scheduling, Allocation and Mapping in a Single Algorithm,Proc. 27th ACM/IEEE Design Automation Conf., pp. 71–76, June 1990.

  37. J. A. Darringer and W. H. Joyner, A new look at logic synthesis, in17th ACM/IEEE Design Automation Conf., pp. 543–549.

  38. S. Davidson et al., Some experiments in local microcode compaction for horizontal machines,IEEE Trans. on Comput., Vol. C-30, No. 7, pp. 460–477, July 1981.

    Google Scholar 

  39. H. Deman, Tutorial on high-level synthesis,Proc. European Design Automation Conf. '90, March 1990.

  40. H. DeMan et al., Cathedral II: A silicon compiler for digital signal processing,IEEE Design & Test of Computers, Vol. 3, No. 6, pp. 13–25, Dec. 1986.

    Google Scholar 

  41. H. DeMan et al., CATHEDRAL II: A synthesis and module generation system for multiprocessor systems on a chip, NATO Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, L'Aqulia, Italy, July 1986.

    Google Scholar 

  42. H. DeMan et al., Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms,Proc. of the IEEE, Vol. 78, No. 2, pp. 319–335, Feb. 1990.

    Google Scholar 

  43. S. Devadas and R. Newton, Algorithms for hardware allocation in data path synthesis,IEEE Trans. on CAD, Vol. 8, No. 7, pp. 768–781, July 1989.

    Google Scholar 

  44. S. W. Director et al., A design methodology and computer aids for digital VLSI systems,IEEE Trans. Circuits Syst., Vol. CAS-28, No. 7, pp. 634–645, July 1981.

    Google Scholar 

  45. N. D. Dutt and D. D. Gajski, Design synthesis and silicon compilation,IEEE Design & Test of Computers, pp. 8–23, Dec. 1990.

  46. N. D. Dutt et al., An intermediate representation for behavioral synthesis,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 14–19, 1990.

  47. J. A. Fisher, Trace scheduling: A technique for global microcode compaction,IEEE Trans. on Comput., Vol. C-30, July 1981.

  48. T. D. Friedman and S. C. Yang, Methods used in an automatic logic design generator (ALERT),IEEE Trans. on Comput., Vol. C-18, pp. 593–614, 1969.

    Google Scholar 

  49. D. D. Gajski and R. H. Kuhn, New VLSI tools,Computer, Vol. 16, No. 12, pp. 11–14, Dec. 1983.

    Google Scholar 

  50. C. H. Gebotys, Optimal synthesis of multichip architectures,Proc. 29th ACM/IEEE Design Automation Conf., pp. 238–241, 1992.

  51. E. F. Girczyc,Automatic Generation of Microsequenced Data Paths to Realize ADA Circuit Descriptions, Ph.D. thesis, Carleton University, Ottawa, Canada, July 1984.

    Google Scholar 

  52. E. F. Girczyc and J. P. Knight, An ADA to standard cell hardware compiler based on graph grammars and scheduling,Proc. ICCAD '84, Oct. 1984.

  53. J. Granacki et al., The ADAM advanced design automation system: Overview, planner and natural language interface, presented at the 22nd ACM/IEEE Design Automation Conf., June 1985.

  54. R. Gupta and G. DeMicheli, Partitioning of Functional Models of Synchronous Digital Systems,Proc. ICCAD '90, pp. 216–219, Santa Clara, CA, Nov. 1990.

  55. R. Gupta and G. DeMicheli, System-level synthesis using Re-programmable components,Proc. European Design Automation Conf. 92, pp. 2–7, 1992.

  56. L. J. Hafer and A. C. Hafer, Register-transfer level digital design automation: The allocation process,Proc. of the 15th ACM/IEEE Design Automation Conf., pp. 213–219, June 1978.

  57. L. J. Hafer and A. C. Parker, Automated synthesis of digital hardware,IEEE Trans. on Comput., Vol. C-31, pp. 93–109, Feb. 1982.

    Google Scholar 

  58. L. J. Hafer and A. C. Parker, A formal method for the specification, analysis, and design of register-transfer level digital logic,IEEE Trans. on CAD, Vol. 2, No. 1, pp. 4–18, Jan. 1983.

    Google Scholar 

  59. A. Hemani and Postula, A neural net based self organising scheduling algorithm,Proc. of the European Design Automation Conf. '90, pp. 136–140, Glasgow, Scotland, March 1990.

  60. C. Y. Hitchcock and D. E. Thomas, A method of automatic data path synthesis,Proc. of the 20th ACM/IEEE Design Automation Conf., pp. 483–489, June 1983.

  61. Y. S. Hsu and Y. L. Lin, High-level synthesis in the THEDA system, inHigh-level VLSI Synthesis, R. Camposano and W. Wolf, eds., Norwell, MA: Kluwer Academic Publishers, 1991, pp. 283–306.

    Google Scholar 

  62. C. Y. Huang et al., Data path allocation based on bipartite weighted matching,Proc. 27th ACM/IEEE Design Automation Conf., pp. 499–504,1990.

  63. K. S. Hwang et al., Workshop on high-level synthesis, Orcas Island, WA, Jan. 1988.

  64. M. Ishikawa and G. De Micheli, A module selection algorithm for high-level synthesis,IEEE Int'l Symposium on Circuits and Systems, Singapore, pp. 1777–1780, June 1991.

  65. R. Jain et al., Predicting system-level area and delay for pipelined and nonpipelined designs,IEEE Trans. on CAD, Vol. 11, No. 8, pp. 955–965, 1992.

    Google Scholar 

  66. S. D. Johnson,Synthesis of Digital Design from Recursion Equations, Ph.D. thesis, Indiana University, 1984, Published, Cambridge, MA: MIT Press, 1984.

    Google Scholar 

  67. J. Jou et al., PASS: A package for automatic scheduling and sharing pipelined data paths,IEEE Int'l Symposium on Circuits and Systems, Singapore, pp. 1769–1772, June 1991.

  68. A. H. G. Rinnooy Kan,Machine Scheduling Problems — Classification, Complexity and Computations, The Hague, The Netherlands: Martinus Mijhoff, 1976.

    Google Scholar 

  69. T. Kim et al., A scheduling algorithm for conditional resource sharing,Proc. 1CCAD '91, pp. 84–87,1991.

  70. D. Knapp et al., An expert synthesis system,Proc. of ICCAD-84, pp. 419–424, Sept. 1984.

  71. D. W. Knapp and A. C. Parker, A design utility manager: The ADAM planning engine,Proc. 23rd ACM/IEEE Design Automation Conf., pp. 48–54, July 1986.

  72. T.J. Kowalski et al., The VLSI design automation assistant: From algorithms to its applications,IEEE Design & Test of Computers, pp. 33–43, Aug. 1985.

  73. T.J. Kowalski,An Artificial Intelligence Approach to VLSI Design, Boston, MA: Kluwer Academic Publishers, 1985.

    Google Scholar 

  74. T. Kowalski, The VLSI design automation assistant: An architecture compiler, inSilicon Compilation, Daniel D. Gajski, ed., pp. 122–152, Reading, MA: Addison-Wesley, 1988.

    Google Scholar 

  75. S. J. Krolikoski, The V-synth system,Proc. COMPCON Spring 88, pp. 328–331, Feb. 1988.

  76. K. Kucukcakar and A. C. Parker, CHOP: A constraint-driven system-level partitioner,Proc. 28th ACM/IEEE Design Automation Conf., pp. 514–519, 1991.

  77. F. J. Kurdahi and A. C. Parker, REAL: A program for REgister ALlocation,Proc. of the 24th ACM/IEEE Design Automation Conf., pp. 210–215, June 1987.

  78. E. Lagnese and D. Thomas, Architectural partitioning for system level design,Proc. 26th ACM/ IEEE Design Automation Conf., pp. 62–67, 1989.

  79. E. L. Lawler et al., Recent developments in deterministic and stochastic scheduling: A survey, inDeterministic and Stochastic Scheduling, M. A. H. Dempster, J. K. Lenstra, and A. H. G. Rinnooy Kan, eds., Dordrecht, Germany: D Reidel, 1982.

    Google Scholar 

  80. J. Lee et al., A new integer linear programming formulation for the scheduling problem in datapath synthesis,Proc. ICCAD '89, Santa Clara, CA, Nov. 1989.

  81. L. Lucke et al., Unfolding and retiming for high-level synthesis,IEEE Int'l Symposium on Circuits and Systems, Singapore, pp. 2351–2354, June 1991.

  82. T. A. Ly et al., A Generalized Interconnect Model for Data Path Synthesis,Proc. 27th ACM/IEEE Design Automation Conf., pp. 168–173, June 1990.

  83. P. Marwedel, A new synthesis algorithm for the MIMOLA software system,Proc. of the 23th ACM/IEEE Design Automation Conf., pp. 271–277, 1986.

  84. M. C. McFarland, The VT: A database for automated digital design, DRC-01-4-80, Design Research Center, Carnegie-Mellon University, Dec. 1978.

  85. M. C. McFarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral description,Proc. of the 23th ACM/IEEE Design Automation Conf., pp. 474–480, June 1986.

  86. M. C. McFarland, A. C. Parker, and R. Camposano, The high-level synthesis of digital systems,Proc. of the IEEE, Vol. 78, No. 2, pp. 301–318, Feb. 1990.

    Google Scholar 

  87. G. D. Micheli and D. C. Ku, Hercules: a system for high-level synthesis,Proc. of the 25th ACM/IEEE Design Automation Conf., pp. 483–488, June 1988.

  88. G. D. Micheli, High-level synthesis of digital circuits,IEEE Design & Test of Computers, pp. 6–7, Oct. 1990.

  89. J. Nestor, Specification and synthesis of digital systems with interfaces, CMUCAD-87-10, Dept. of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA, April 1987.

    Google Scholar 

  90. A. Nicolau, Percolation scheduling: A parallel compilation technique, Ithaca, NY: Dept. of Computer Science, Cornell University, TR 85-678, May 1985.

    Google Scholar 

  91. B. Pangrle and D. Gajski, Slicer: A state synthesizer for intelligent silicon compilation,Proc. ICCAD, Rye Brook, NY, pp. 42–45, Oct. 1987.

  92. B. M. Pangrle, Splicer: A heuristic approach to connectivity binding,Proc. of the 25th ACM/IEEE Design Automation Conf., pp. 536–541, June 1988.

  93. N. Park and A. C. Parker, SEHWA: A software package for synthesis of pipelines from behavioral specifications,IEEE Trans. on CAD, Vol. 7, No. 3, pp. 356–370, March 1988.

    Google Scholar 

  94. A. C. Parker et al., MAHA: A program for datapath synthesis,Proc. of the 23th ACM/IEEE Design Automation Conf., pp. 263–270, 1986.

  95. P. G. Paulin et al., HAL: A multi-paradigm approach to automatic data path synthesis,Proc. of the 23th ACM/IEEE Design Automation Conf., pp. 263–270, 1986.

  96. P. G. Paulin and J. P. Knight, Force-directed scheduling in automatic data path synthesis,Proc. of the 24th ACM/IEEE Design Automation Conf., pp. 195–202, 1987.

  97. P.G. Paulin and J.P. Knight, Algorithms for high-level synthesis,IEEE Design & Test of Computers, pp. 18–31, Dec. 1989.

  98. P. G. Paulin, Force-directed scheduling for the behavioral synthesis of ASIC's,IEEE Trans. on CAD, Vol. 8, No. 6, pp. 661–679, June 1989.

    Google Scholar 

  99. P. G. Paulin and J. P. Knight, Behavioral description languages,IEEE Design & Test of Computers, pp. 56–62, Feb. 1990.

  100. P. G. Paulin, Global scheduling and allocation algorithms in the HAL system, inHigh-Level VLSI Synthesis, R. Camposano and W. Wolf, eds., pp. 255–281, Norwell, MA: Kluwer Academic Publishers, 1991.

    Google Scholar 

  101. Z. Peng, Synthesis of VLSI systems with the CAMAD design aid,Prof. of the 23th ACM/IEEE Design Automation Conf., pp. 278–284, June 1986.

  102. R. Potasaman et al., Percolation based synthesis,Proc. 27th ACM/IEEE Design Automation Conf., pp. 444–449, June 1990.

  103. J. V. Rajan and D. E. Thomas, Synthesis by delayed binding of decisions,Proc. of the 22th ACM/IEEE Design Automation Conf., pp. 367–373, June 1985.

  104. J. V. Rajan,Automatic Synthesis of Microprocessors, Ph.D. thesis, Carnegie-Mellon University, Pittsburgh, PA, Dec. 1988.

    Google Scholar 

  105. M. Rim and R. Jain, Representing conditional branches for high-level syntheis applications,Proc. 29th ACM/IEEE Design Automation Conf., pp. 106–111, 1992.

  106. W. Rosenstiel, Synthese des Datenflusses digitaler Schaltungen aus formalen Spezifikationen, Ph.D. dissertation, Fakultät für Informatik, Univ. Karlsruhe, VDI-Verlag, 1984.

  107. W. Rosenstiel, Optimizations in High Level Synthesis,Microprocessing and Microprogramming (18), pp. 543–549, North-Holland, 1986.

  108. W. Rosenstiel and H. Kramer, Scheduling and Assignment in High Level Synthesis, inHigh-Level VLSI Synthesis, R. Camposano and Wayne Wolf, eds., Norwell, MA: Kluwer, 1991.

    Google Scholar 

  109. E.A. Rudensteiner and D.D. Gajski, Functional synthesis using area and delay optimization,Porc. 29th ACM/IEEE Design Automation Conf., pp. 291–296, 1992.

  110. R. C. Sarma, M. D. Dooley, N. C. Newman, and G. Hetherington, High-level synthesis: Technology transfer to industry,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 549–554, 1990.

  111. J. Scheichenzuber et al., Global hardware synthesis from behavioral dataflow descriptions,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 456–461, 1990.

  112. M. Shih et al., Performance-driven system partitioning on multi-chip modules,Proc. 29th ACM/IEEE Design Automation Conf., pp. 53–56, 1992.

  113. E. A. Snow et al., A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs,Proc. of the 15th ACM/IEEE Design Automation Conf., pp. 220–226,1978.

  114. E. A. Snow,Automation of Module Set Independent Register-transfer Level Design, Ph.D. thesis, Carnegie-Mellon University, Pittsburgh, PA, April 1978.

    Google Scholar 

  115. E. A. Snow, Design representation and transformation in the system architect's workbench,Proc. ICCAD-87, pp. 166–169, Nov. 1987.

  116. L. Stok, Interconnect optimization during data path allocation, inProc. European Design Automation Conf. '90, Glasgow, Scotland, pp. 141–145, March 1990.

  117. T. Tanaka, T. Kobayshi, and O. Karatsu, Harp: Fortran to silicon,IEEE Trans. on CAD, Vol. 8, No. 6, pp. 649–660, June 1989.

    Google Scholar 

  118. D. E. Thomas et al. The system architect's workbench,Proc. of the 25th ACM/IEEE Design Automation Conf., pp. 337–343, June 1988.

  119. L. Trevillyan, An overview of logic synthesis systems,Proc. of the 24th ACM/IEEE Design Automation Conf., pp. 166–172, June 1987.

  120. H. Trickey, Flamel: A high-level hardware compiler,IEEE Trans. on CAD, Vol. CAD-6, No. 2, pp. 259–269, March 1987.

    Google Scholar 

  121. F.S. Tsai and Y.C. Hsu, Data path construction and refinement,Proc. ICCAD '90, pp. 308–311, 1990.

  122. F.S. Tsai and Y.C. Hsu, STAR: An automatic data path allocator,IEEE Trans. on CAD, Vol. 11, No. 9, pp. 1053–1064, 1990.

    Google Scholar 

  123. C. J. Tseng and D. P. Siewiorek, Automated synthesis of data paths in digital systems,IEEE Trans. on CAD, Vol. CAD-5, pp. 379–395, July 1986.

    Google Scholar 

  124. C. J. Tseng et al., Bridge: A versatile behavioral synthesis system,Proc. 25th ACM/IEEE Design Automation Conf., pp. 415–420, 1988.

  125. F. Vahid and D.D. Gajski, Specification partitioning for system design,Proc. 29th ACM/IEEE Design Automation Conf., pp 219–224, 1992.

  126. K. Wakabayashi and T. Yoshimura, A resource sharing control synthesis method for conditional branches,Proc. ICCAD '89, Santa Clara, CA, pp. 62–65, Nov. 1989.

  127. R. A. Walker and D. E. Thomas, Design representation and transformation in the system architect's workbench, Proc. ofICCAD-87, pp. 166–169, 1987.

  128. R. A. Walker,Design Representation and Behavioral Transformation for Algorithmic Level Integrated Circuit Design, Ph.D. dissertation, Carnegie-Mellon University, Pittsburgh, PA, April 1988.

    Google Scholar 

  129. R. A. Walker and D. E. Thomas, Behavioral transformation for algorithmic level,IEEE Trans. on CAD, Vol. 8, pp. 1115–1128, Oct. 1989.

    Google Scholar 

  130. R.A. Walker and R. Camposano,A Survey of High-level Synthesis Systems, Norwell, MA: Kluwer Academic Publishers, 1991.

    Google Scholar 

  131. C. Y. Wang and K. Parhi, High level DSP synthesis using the MARS design system,IEEE Int'l Symposium on Circuits and Systems, San Diego, CA, pp. 164–167, May 1992.

  132. G. S. Whitcomb and A. R. Newton, Abstract data types and high-level synthesis,Proc. of the 27th ACM/IEEE Design Automation Conf., pp. 680–685, 1990.

  133. W. Wolf, A catalog of optimizations for the behavioral synthesis of control-dominated machines,Proc. ACM/IEEE Workshop on High-Level Synthesis, Kennebunkport, ME, Oct. 1989.

  134. A.C. Wu et al., Layout-area models for high-level synthesis,Proc. ICCAD '91, pp. 34–37, 1991.

  135. G. Zimmermann, MDS-The MIMOLA design method,J. Digital Systems, Vol. 4, No. 3, pp. 337–369, 1980.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, Utah State University, 84322-4205, Logan, Utah

    H. D. Cheng & C. Xia

Authors
  1. H. D. Cheng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. C. Xia
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Cheng, H.D., Xia, C. High-level synthesis: current status and future prospects. Circuits Systems and Signal Process 14, 351–400 (1995). https://doi.org/10.1007/BF01189017

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01189017

Keywords

Search

Navigation