Abstract
In this paper a fully systolic, bit level, three-port unconstrained adaptor, which constitutes the main nontrivial building block of ladder wave digital filters, is generated. The one-dimensional binary convolution is used as the underlying algorithm for the implementation of a multiplication. The Isb-first input data organization approach is adopted and thecanonical mapping methodology is used to fully systolize the unconstrained parallel three-port adaptor at the bit level with piplining period a=1. The technique is based on a transformation of the adaptor's signal-flow graph, so that unidirectional data flow takes place. A ring-systolic scheme is proposed for implementing communications among adaptors.
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References
A. Fettweis, Design of orthogonal and related digital filters by network theory approach,Archiv für Elektronik und Übertragungstechnik (AEU), vol. 44, No. 2, pp. 65–74, March–April 1990.
A. Fettweis, Wave digital filters: Theory and practice,Proc. IEEE, vol. 74, No. 2, Feb. 1986.
A. Fettweis, Digital filters related to classical filter networks,Archiv für Elektronik und Übertragungstechnik (AEU), vol. 25, pp. 79–89, Feb. 1971.
S. Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.
H.T. Kung, Why systolic architectures,IEEE Computer Magazine, vol. 15, pp. 37–46, Jan. 1982.
S.Y. Kung, On supercomputing with systolic/wavefront array processors,Proc. IEEE, vol. 72, pp. 865–884, July1984.
S. Lawson and S. Summerfield, The design of wave digital filters using fully pipelined bit-level systolic arrays,VLSI Signal Processing, vol. 2, pp. 51–64, 1990.
H.H. Lu, E.A. Lee, and D.G. Messerschmitt, Fast recursive filtering with multiple slow processing elements,IEEE Trans, on Circuits Syst., vol. CAS-32, No. 11, pp. 1119–1129, Nov. 1985.
B.G. Mertzios, Fast implementation of multivariable linear systems via VLSI array processors,COMPEL-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, vol. 10, No. 1, pp. 1–10, 1991.
B.G. Mertzios, Fast block implementation of two-dimensional recursive digital filters via VLSI array processors,Archiv für Elektronik und Übertragungstechnik (AEU), vol. 44, pp. 55–58, 1990.
B.G. Mertzios and S.S. Scarlatos, On the systolic implementation of wave digital filters,Archiv für Elektronik und Übertragungstechnik (AEU), vol. 45, No. 6, pp. 335–343, Nov.–Dec. 1991.
B.G. Mertzios, S.S. Scarlatos, and A.N. Venetsanopoulos, Systolic arrays for ladder wave digital filters,Proc. Int. Conf. on Digital Signal Processing, pp. 8–13, Florence, Italy, Sept. 1991.
B.G. Mertzios and A.N. Venetsanopoulos, Implementation of quadratic digital filters via VLSI array processors,Archiv für Elektronik und Übertragungstechnik (AEU), vol. 43, No. 3, 153–157, 1989.
K.K. Parhi and D.G. Messerschmitt, Pipeline interleaving and parallelism in recursive digital filters, Part I: Pipelining using scattered look-ahead and decomposition, and Part II: Pipelined incremental block filtering,IEEE Trans, on Acoust. Speech, and Signal Process., vol. 37, No. 7, pp. 1099–1134, July 1989.
N. Petrie, The design and implementation of digital wave filter adaptors, Ph.D. thesis, University of Edinburgh, 1985.
S.K. Rao and T. Kailath, VLSI arrays for signal processing,IEEE Trans. on Circuits Syst., vol. CAS-32, No. 11, pp. 1105–1118, Nov. 1985.
R.J. Singh, J.V. McCanny, and R.F. Woods, Pipelined two-port adaptor for wave digital filtering,Proc. IEEE Intern. Conf. on Acoust., Speech and Signal Process., vol. 2, pp. 1033–1036, 1990.
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Mertzios, B.G. Pipelining the unconstrained three-port wave filter adaptor at the bit level. Circuits Systems and Signal Process 14, 285–298 (1995). https://doi.org/10.1007/BF01189014
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DOI: https://doi.org/10.1007/BF01189014