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Implementation of matrix decomposition structures of 2-D digital filters via VLSI array processors

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Abstract

This paper describes an implementation of 2-D FIR and IIR linear digital filters via VLSI array processors. The underlying realization structures are based on the matrix decomposition approach. The 2-D concurrent processing is used in order to implement the row and column delays within the cycle time. A high degree of concurrency is achieved by exploiting the pipelining of the array processors with the inherent parallelism of the matrix decomposition structure. The resulting structures are modular, and regular, use only local communication and internal local feedback loops, and achieve high throughput and sampling rates.

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Authors and Affiliations

  1. Department of Electrical & Computer Engineering, Democritus University of Thrace, 67 100, Xanthi, Hellas

    B. G. Mertzios

  2. Department of Electrical & Computer Engineering, University of Toronto, M5S 1A4, Toronto, Canada

    A. N. Venetsanopoulos

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  1. B. G. Mertzios
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  2. A. N. Venetsanopoulos
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Mertzios, B.G., Venetsanopoulos, A.N. Implementation of matrix decomposition structures of 2-D digital filters via VLSI array processors. Circuits Systems and Signal Process 14, 39–55 (1995). https://doi.org/10.1007/BF01183747

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