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Check of linear combination circuits

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Literature Cited

  1. V. M. Glushkov, Synthesis of Digital Automata [in Russian], Fizmatgiz, Moscow (1962).

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  2. M. A. Breuer, “Generation of fault tests for linear logic networks,” IEEE Trans. Comput.,C- 21, No. 1 (1972).

  3. S. M. Reddy, “Easily testable realizations for logic functions,” IEEE Trans. Comput.,C- 21, No. 1 (1972).

  4. K. K. Saluja and S. M. Reddy, “Fault detecting test set for Reed-Muller canonic networks,” IEEE Trans. Comput.,C- 24, No. 10 (1975).

  5. M. N. Vasilenko, V. V. Sapozhnikov, and Vl. V. Sapozhnikov, “Reducing the list of single faults when constructing tests for combination circuits,” Avtom. Telemekh., No. 8 (1974).

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Authors
  1. V. V. Sapozhnikov
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Translated from Kibernetika, No. 3, pp. 44–47, May–June, 1979.

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Sapozhnikov, V.V. Check of linear combination circuits. Cybern Syst Anal 15, 341–345 (1979). https://doi.org/10.1007/BF01075093

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  • DOI: https://doi.org/10.1007/BF01075093

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