Journal of Electronic Testing

, Volume 7, Issue 1–2, pp 115–124 | Cite as

Partial scan design and test sequence generation based on reduced scan shift method

  • Yoshinobu Higami
  • Seiji Kajihara
  • Kozo Kinoshita
Test Length Minimization

Abstract

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.

Keywords

scan design test sequence generation partial scan circuit short test sequence reduced scan shift 

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Copyright information

© Kluwer Academic Publishers 1995

Authors and Affiliations

  • Yoshinobu Higami
    • 1
  • Seiji Kajihara
    • 1
  • Kozo Kinoshita
    • 1
  1. 1.Department of Applied Physics, Faculty of EngineeringOsaka UniversitySuita, 565 OsakaJapan

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