Journal of Electronic Testing

, Volume 5, Issue 4, pp 367–376 | Cite as

On-chip testing of random access memories

  • Kewal K. Saluja
Article

Abstract

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.

Keywords

BIST RAM Built-In Self-Test pattern sensitive faults RAM testing reconfigured random access memories test architectures test parallelism 

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Copyright information

© Kluwer Academic Publishers 1994

Authors and Affiliations

  • Kewal K. Saluja
    • 1
  1. 1.Department of Electrical and Computer EngineeringThe University of Wisconsin-MadisonMadisonUSA

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