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Journal of Electronic Testing

, Volume 4, Issue 4, pp 345–360 | Cite as

Fault simulation of linear analog circuits

  • Naveena Nagi
  • Abhijit Chatterjee
  • Jacob A. Abraham
Article

Abstract

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.

Keywords

Test Generation Analog Circuit Input Test Circuit Simulator Analog Behavior 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1993

Authors and Affiliations

  • Naveena Nagi
    • 1
  • Abhijit Chatterjee
    • 2
  • Jacob A. Abraham
    • 3
  1. 1.Computer Engineering Research CenterUniversity of Texas at AustinAustin
  2. 2.School of Electrical EngineeringGeorgia Institute of TechnologyAtlanta
  3. 3.Computer Engineering Research CenterUniversity of Texas at AustinAustin

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