Abstract
There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
B. Konemann, J. Mucha, and G. Zwiehoff, “Built-in logic block observation technique,” inProc. Int. Test Conf., pages 37–41, October 1979.
M.S. Abadir and M.A. Breuer, “A knowledge based system for designing testable VLSI chips,”IEEE Design and Test of Computers, vol. 3, pp. 56–68, August 1985.
K. Kim, J.G. Tront, and D.S. Ha, “BIDES: A BIST design expert system,”J. of Electronic Testing: Theory and Applications, vol. 2, pp. 165–179, June 1991.
G. Craig, C. Kime, and K. Saluja, “Test scheduling and control for VLSI built-in self-test,”IEEE Trans. on Computers, vol. C-37, pp. 1099–1109, September 1988.
C.H. Chen, “Graph partitioning for concurrent test scheduling in VLSI circuit,” inProc. 28th Design Automation Conf., pp. 287–290, June 1991.
W.B. Jone, C.A. Papachristou, and M. Pereira, “A scheme for overlaying concurrent testing of VLSI circuits,” inProc. 26th Design Automation Conf., pp. 531–536, June 1989.
S.P. Lin, C.A. Njinda, and M.A. Breuer, “A systematic approach for designing testable VLSI circuits,” inProc. ICCAD, pp. 496–499, November 1991.
S.P. Lin, C.A. Njinda, and M.A. Breuer, “A systematic approach for designing testable VLSI circuits,” Technical Report Tech. Report CRI-91-18, University of Southerm California, July 1991.
K. Kucukcakar and A.C. Parker, “MABAL: A software package for Module and Bus Allocation,”Int. J. of Computer Aided VLSI Design, vol. 2, no. 4, pp. 419–426, 1990.
S.P. Lin, “A testable design system using BILBO-oriented methodologies,” University of Southern California, Department of EE-Systems, July 1992, Ph.D. Thesis Proposal.
L.T. Wang and E.J. McCluskey, “Built-in self-test for sequential machines,” inProc. Int'l. Test Conf., pp. 334–341, September 1987.
K. Hwang and F.A. Briggs,Computer Architecture and Parallel Processing. New York: McGraw-Hill, 1984.
Rajiv Gupta, W.H. Cheng, Rajesh Gupta, I. Hardonag, and M.A. Breuer, “An object-oriented VLSI CAD framework: A case study in rapid prototyping,”IEEE Computer, pp. 28–37, May 1989.
Z.-A. Zhu and M.A. Breuer, “A knowledge-based system for selecting test methodologies,”IEEE Design & Test of Computers, vol. 5, pp. 41–59, October 1988.
S.P. Lin, M.A. Breuer, and C.A. Njinda, “A self-adaptive expert selection system (SAESS) and its application to selection problems,” inProc. Third Int'l Conf. on Software Eng. and Knowledge Eng., pp. 116–121, June 1991.
M. McFarland, A. Parker, and R. Camposano, “Tutorial on high-level synthesis,” inProc. 25th Design Automation Conf., pp. 330–336, July 1988.
M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design. New York, NY: W.H. Freeman and Company, 1990.
A. Majumdar and S. Sastry, “Test length prediction in random testing of combinational circuits,” private communication.
Author information
Authors and Affiliations
Additional information
This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.
Rights and permissions
About this article
Cite this article
Lin, SP., Njinda, C.A. & Breuer, M.A. Generating a family of testable designs using the BILBO methodology. J Electron Test 4, 71–89 (1993). https://doi.org/10.1007/BF00971941
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00971941