Journal of Electronic Testing

, Volume 4, Issue 1, pp 71–89 | Cite as

Generating a family of testable designs using the BILBO methodology

  • Sen-Pin Lin
  • Charles A. Njinda
  • Melvin A. Breuer
Article

Abstract

There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.

Keywords

BILBO design system built-in self-test synthesis for testability test scheduling 

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Copyright information

© Kluwer Academic Publishers 1993

Authors and Affiliations

  • Sen-Pin Lin
    • 1
  • Charles A. Njinda
    • 1
  • Melvin A. Breuer
    • 1
  1. 1.Department of Electrical Engineering-SystemsUniversity of Southern CaliforniaLos Angeles

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