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FFT computation with linear processor arrays using a data-driven control scheme

  • Ding-Ming Kwai
  • Behrooz Parhami
Article

Abstract

For a large numberN of data points, linear FFT arrays consisting of Θ(log2N) processors provide significant economy in hardware. In this paper we discuss the radix-2 decimation-in-frequency Cooley-Tukey algorithm implemented on linear arrays, thereby allowing a continuous real-time application using a word-serial input data stream to the linear arrays. In order to avoid memory access and data path switching under central control, we present a novel data-driven scheme permitting the proposed linear arrays to correctly operate on arbitrarily arriving signal sequences. This distributed control scheme incorporates a control signal propagated with the data signals, in the form of a tag attached to data items. The tag provides control information to initiate the access to the memory containing the coefficients and to select and appropriate data path so that regular data flow can be achieved within the linear array. The cascade structures are well suited for the computation and can operate in pipeline fashion at extremely high data rates. The proposed data-driven control scheme can be used with both synchronous and asynchronous (wavefront) processor arrays.

Keywords

Data Item Linear Array Shift Register Systolic Array Fast Fourier Transform Computation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    C.D. Thompson, “Fourier transform in VLSI”,IEEE Transactions on Computers, Vol. C-32 pp. 1047–1057, 1983.CrossRefMATHGoogle Scholar
  2. 2.
    H.T. Kung and C.E. Leiserson, “Algorithms for VLSI processor arrays,” inIntroduction to VLSI Systems, C. Mead and L. Conway (eds.), Reading, MA: Addison-Wesley, pp. 271–292, 1980.Google Scholar
  3. 3.
    C. Van Loan,Computational Franeworks for the Fast Fourier Transform, Philadelphia, PA: Society for Industrial and Applied Mathematics, 1992.CrossRefGoogle Scholar
  4. 4.
    A.L. Fisher and H.T. Kung, “Synchronizing large VLSI processor arrays”IEEE Transactions on Computers, Vol. C-34, pp. 734–740, 1985.CrossRefGoogle Scholar
  5. 5.
    R. Gupta, R. Gupta, and M.A. Breuer, “The BALLAST methodology for structured partial scan design,”IEEE Transactions on Computers, Vol. 39, pp. 538–544, 1990.CrossRefGoogle Scholar
  6. 6.
    K. Yamashita et al., “A wafer-scale 170000-gate FFT processor with built-in test circuits,”IEEE Journal of Solid-State Circuits, Vol. 23, pp. 336–342, 1988.CrossRefGoogle Scholar
  7. 7.
    J. Choi and V. Boriakoff, “A new linear systolic array for FFT computation,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Vol. 39, pp. 236–239, 1992.CrossRefMATHGoogle Scholar
  8. 8.
    V. Boriakoff, “FFT computation with systolic arrays, a new architecture,”IEEE Transactions on Circuits and Systems—II: Analog and Digital Signal Processing, Vol. 41, pp. 278–284, 1994.CrossRefGoogle Scholar
  9. 9.
    M. Aloqeely and C.Y. Chen, “Sequencer-based data path synthesis of regular iterative algorithms,”Proc. 31st ACM/IEEE Design Automation Conf., pp. 155–160, 1994.Google Scholar
  10. 10.
    D.-M. Kwai and B. Parhami, “A data-driven control scheme for linear processor arrays,” Submitted for publication.Google Scholar
  11. 11.
    H.L. Groginsky and G.A. Works, “A pipeline fourier transform,”IEEE Transactions on Computers, Vol. 19, pp. 1015–1019, 1970.CrossRefGoogle Scholar
  12. 12.
    S. Sarkar and A.K. Majumdar, “Fast fourier transform using linear tagged systolic array,”IEEE Region 10 Conf. Computer and Communication Systems, pp. 289–293, 1990.Google Scholar
  13. 13.
    D. Audet, Y. Savaria, and N. Arel, “Pipelining communications in large VLSI/ULSI systems,”IEEE Trans. Very Large Integration (VLSI) Systems, Vol 2, pp. 1–10, 1994.CrossRefGoogle Scholar
  14. 14.
    M.O. Ahmad and D.V. Poornalah, “Design of an efficient VLSI inner-product processor for real-time DSP applications,”IEEE Transactions on Circuits and Systems, Vol. 36, pp. 324–329, 1989.MathSciNetCrossRefGoogle Scholar
  15. 15.
    S.Y. Kung, “On supercomputing with systolic/wavefront array processors,”Proceedings IEEE Vol. 72, pp. 867–884, 1984.CrossRefGoogle Scholar
  16. 16.
    S.Y. Kung,VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.Google Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Ding-Ming Kwai
    • 1
  • Behrooz Parhami
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of CaliforniaSanta BarbaraUSA

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