Skip to main content
SpringerLink
Log in

Dynamic programming implementation on array processor architectures

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. R. Bellman,Applied Dynamic Programming, Princeton University Press, 1962.

  2. D.H. Ballard and C.M. Brown,Computer Vision, Prentice Hall, 1982.

  3. A.J. Viterbi, “Error bounds for convolution codes and an asymptotically optically optimal decoding algorithm”IEEE Trans. on Information Theory, Vol. IT-13, pp. 260–269, Apr. 1967.

    Article  MATH  Google Scholar 

  4. L.R. Rabiner and B.H. Juang, “An introduction to hidden Markov models,”IEEE ASSP Magazine, Vol. 3, No. 1, pp. 4–16, Jan. 1986.

    Article  Google Scholar 

  5. D.J. Burr, B.D. Ackland, and N. Weste, “Array configurations for dynamic time warping,”IEEE Trans. on ASSP, Vol. ASSP-32, No. 1, pp. 119–128, Feb. 1984.

    Article  Google Scholar 

  6. R. Kavaler, R.W. Brodersen, T.G. Noll, M. Lowy, and H. Murveit, “A dynamic time warp IC for a one thousand word recognition system,”Proc. of ICASSP'84, pp. 25B.6.1–25B.6.4, 1984.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, GR-54006, Thessaloniki, Greece

    K. I. Diamantaras

  2. Auspy Development Inc., 10430 S. De Anza Blvd., Suite 275, 95014, Cupertino, CA

    W. H. Chou

  3. Department of Electrical Engineering, 08544, Princeton, NJ, USA

    S. Y. Kung

Authors
  1. K. I. Diamantaras
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. W. H. Chou
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. S. Y. Kung
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Diamantaras, K.I., Chou, W.H. & Kung, S.Y. Dynamic programming implementation on array processor architectures. J VLSI Sign Process Syst Sign Image Video Technol 13, 27–35 (1996). https://doi.org/10.1007/BF00930665

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00930665

Keywords

Search

Navigation