Abstract
In this paper the problems involved with high-level synthesis of ASIC regular arrays for real-time signal processing systems will be outlined. It will be shown that novel nonlinear, behavior preserving, transformations and extended affine mapping techniques are of key importance in mapping nonuniform recurrence equations on regular arrays with realistic constraints on area, throughput and I/O bandwidth.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
F. Catthoor, J. Rabaey, H. De Man, “Target architectures in the Cathedral synthesis systems: objectives and design experience,”IEEE International Symposium on Circuits and Systems, 1989, pp. 1907–1910.
R.M. Karp, R.E. Miller, S. Winograd, “The organization of computations for uniform recurrence equations,”Journal of the ACM, vol. 14, 1967, pp. 563–590.
P. Quinton, V. van Dongen, “The mapping of linear recurrence equations on regular arrays,”Journal of VLSI Signal Processing, vol. 1. 1989, pp. 95–113.
A. Benaini, P. Quinton, Y. Robert, Y. Saouter, B. Tourancheau. “Synthesis of a new systolic architecture for the algebraic path problem,”Science of Computer Programming, 1990, pp. 135–158.
M.F.X.B. van Swaaij, F.V.M. Catthoor, H.J. De Man, “Deriving ASIC architectures for the Hough Transform,”Parallel Computing, 16, 1990, pp. 113–121.
D.I. Moldovan, “Advis: a software package for the design of systolic arrays,”IEEE International Conference on Computer Design, 1984, pp. 158–164.
J. Rosseel, F. Catthoor, H. De Man, “Extensions to linear mapping on regular arrays with complex processing elements,”IEEE International Conference on Application Specific Array Processors, 1990, pp. 156–167.
P. Hilfinger, J. Rabaey, D. Genin, C. Scheers, H. De Man, “DSP specification using the SILAGE language,” to be published in the proceedings of:IEEE International Conference on Acoustics, Speech, and Signal Processing, 1990, pp. 1057–1060.
D. Lanneer, F. Catthoor, G. Goossens, M. Pauwels, J. Van Meerbergen, H. De Man, “Open-ended system for high-level synthesis of flexible signal processors,”European Design Automation Conference, 1990, pp. 272-276.
S.V. Rajopadhye, R.M. Fujimoto, “Systolic array design by static analysis of program dependencies,”Parallel Architectures and Languages Europe, (J. De Bakker, A.J. Nyman, and P.C. Treleaven eds.) Springer-Verlag, 1987, pp. 295–310.
Y. Wong, J-M. Delosme, “Optimal systolic implementations ofN-dimensional recurrences,”IEEE International Conference on Computer Design, 1985, pp. 618–621.
J. Annevelink, P. Dewilde, “Hifi: A functional design system for VLSI processing arrays,”IEEE International Conference on Systolic Arrays, 1988, pp. 413–452.
P. Quinton, “Automatic synthesis of systolic arrays from recurrent uniform equations,”Proc. 11th International Symposium on Computer Architecture, 1984, pp. 208–214.
J.A.B. Fortes, D.I. Moldovan, “Parallelism detection and transformation techniques useful for VLSI algorithms,”Journal of Parallel and Distributed Computing, vol. 2, 1985 pp. 277–301.
H. Nelis, Ed F. Deprettere, “A systematic method of mapping algorithms of arbitrarily large dimensions onto fixed size systolic arrays,”IEEE International Symposium on Circuits and Systems, 1987, pp. 559–563.
S.K. Rao, T. Kailath, “Architecture design for regular iterative algorithms,”Systolic Signal Processing Systems, (E.E. Swartzlander ed.), New York: Marcel Dekker, 1987, pp. 209–297.
Y. Yaacoby, P.R. Cappello, “Scheduling a system of affine recurrence equations onto a systolic array,”IEEE International Conference on Systolic Arrays, 1988, pp. 373–382.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Van Swaaij, M., Rosseel, J., Catthoor, F. et al. Synthesis of ASIC regular arrays for real-time image processing systems. J VLSI Sign Process Syst Sign Image Video Technol 3, 183–192 (1991). https://doi.org/10.1007/BF00925829
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/BF00925829