VHDL-based rapid system prototyping

  • T. Egolf
  • M. Pettigrew
  • J. DeBardelaben
  • R. Hezar
  • S. Famorzadeh
  • A. Kavipurapu
  • M. Khan
  • Lan-Rong Dung
  • K. Balemarthy
  • N. Desai
  • V. Madisetti


The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.


Clock Cycle Virtual Prototype Inverse Discrete Cosine Transform Signal Processing System Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    M.A. Richards, “The rapid prototyping of application specific signal processors (RASSP) program: Overview and accomplishments,”Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug. 1994, pp. 1–8. URL: P.Google Scholar
  2. 2.
    W. Hood, M. Hoffman, J. Malley et al., “RASSP program overview,”Proceedings 2nd Annual RASSP conference, Arlington, VA, July 24–27, 1995, pp. 1–18. URL: http:// Scholar
  3. 3.
    J.E. Saultz, “Lockheed Martin advanced technology laboratories RASSP second year overview,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 19–31. URL: saultz.Google Scholar
  4. 4.
    V. Madisetti, J. Corley, and G. Shaw, “Rapid prototyping of application-specific signal processors: Educator/facilitator current practice (1993) model and challenges,”Proceedings 2nd Annual RASSP Conference, July 1995. URL: http://rassp. Scholar
  5. 5.
    V.K. Madisetti and T.W. Egolf, “Virtual prototyping of embedded microcontroller-based DSP systems,”IEEE Micro, Oct. 1995.Google Scholar
  6. 6.
    ANSI/IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual (1-55937-376-8), Order Number [SH16840].Google Scholar
  7. 7.
    D. Thomas, J. Adams, and H. Schmit, “A model and methodology for hardware-software codesign,”IEEE Design & Test of Computers, pp. 6–15, Sept. 1993.Google Scholar
  8. 8.
    S. Kumar, J. Aylor, B. Johnson, and W. Wulf, “A frame work for hardware/software codesign,”Computer, pp. 39–45, Dec. 1993.Google Scholar
  9. 9.
    R. Gupta and G. De Micheli, “Hardware-software cosynthesis for digital systems,”IEEE Design & Test of Computers, Sept. 1993.Google Scholar
  10. 10.
    A. Kalavade and E. Lee, “A hardware-software codesign methodology for DSP applications,”IEEE Design & Test of Computers, pp. 16–28, Sept. 1993.Google Scholar
  11. 11.
    A. Kalavade and E. Lee, “A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem,”Proc. of the Third International Workshop on Hardware/Software Codesign, Sept. 1994Google Scholar
  12. 12.
    T. Ismail and A. Jerraya, “Synthesis steps and design models for codesign,”Computer, pp. 44–52, Feb. 1995.Google Scholar
  13. 13.
    D. Gajski and F. Vahid, “Specification and design of embedded hardware-software systems,”IEEE Design & Test of Computers, pp. 53–67, Spring 1995.Google Scholar
  14. 14.
    J. DeBardelaben and V. Madisetti, “Hardware/software codesign for signal processing systems—A survery and new results,”Proc. of the 29th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 1995.Google Scholar
  15. 15.
    IEEE Std. 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) (1-55937-299-0), Order Number [SH16097].Google Scholar
  16. 16.
    C. Hein, T. Carpenter, P. Kalutkiewicz, and V. Madisetti, “RASSP VHDL modeling terminology and taxonomy—Revision 1.0,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 273–281. URL: http:// Scholar
  17. 17.
    A.H. Anderson et al., “VHDL executable requirements,”Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug., 1994, pp. 87–90. URL: Scholar
  18. 18.
    G.A. Shaw and A.H. Anderson, “Executable requirements: Opportunities and impediments,”IEEE Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, Atlanta, GA, May 7–10, 1996. pp. 1232–1235.Google Scholar
  19. 19.
    G.A. Frank, J.R. Armstrong, and F.G. Gray, “Support for modelyear upgrades in VHDL test benches,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 211–215. URL: Scholar
  20. 20.
    ISO/IEC 11172, “Information technology—Coding of moving picture and associated audio for digital storage media at up to about 1.5 Mbit/s,” 1993.Google Scholar
  21. 21.
    L.A. Rowe, K. Patel et al., “mpeg_encode/mpeg_play,” Version 1.0, available via anonymous ftp at, Computer Science Department-EECS University of California at Berkeley, May, 1995.Google Scholar
  22. 22.
    ISO/IEC 13818, Coding of Moving Pictures and Associated Audio, Nov. 1993.Google Scholar
  23. 23.
    O. Tanir and others, “A specification-driven architectural design environment,”Computer, pp. 26–35, June 1995.Google Scholar
  24. 24.
    F. Vahid and others, “SpecCharts: A VHDL front-end for embedded systems,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 694–706, June 1995.Google Scholar
  25. 25.
    T.W. Egolf, S. Famorzadeh, and V.K. Madisetti, “Fixed-point codesign in DSP,”VLSI Signal Processing Workshop, Vol. 8, Fall 1994.Google Scholar
  26. 26.
    Naval Research Laboratory, “Processing graph method tutorial,” Jan. 8, 1990.Google Scholar
  27. 27.
    C.R. Robbins, “Autocoding in Lockheed Martin ATL-Camden RASSP hardware/software codesign,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, pp. 129–133, URL: Scholar
  28. 28.
    C.R. Robbins, “Autocoding: An enabling technology for rapid prototyping,”IEEE Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, Scholar
  29. 29.
    System-Level Design Methodology For Embedded Signal Processors, URL: Scholar
  30. 30.
    Publications of the DSP Design Group and the Ptolemy Project, URL: Scholar
  31. 31.
    B. Boehm,Software Engineering Economics, Prentice-Hall Inc., Englewood Cliffs, NJ, 1981.MATHGoogle Scholar
  32. 32.
    V. Madisetti and T. Egolf, “Virtual prototyping of embedded microcontroller-based DSP systems.”IEEE Micro, Oct. 1995.Google Scholar
  33. 33.
    U.S. Air Force Analysis Agency,REVIC Software Cost Estimating Model User's Manual Version 9.2, Dec. 1994.Google Scholar
  34. 34.
    C. Fey, “Custom LSI/VLSI chip design productivity,”IEEE Uournal of Solid-State Circuits, Vol. sc-20, No. 2, April 1985.Google Scholar
  35. 35.
    D. Paraskevopoulos and C. Fey, “Studies in LSI technology economics III: Design schedules for application-specific integrated circuits,”IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 2, April 1987.Google Scholar
  36. 36.
    J. Liu, “Detailed model shows FPGAs' true costs,”EDN, pp. 153–158, May 11, 1995.Google Scholar
  37. 37.
    A. Brooke, D. Kendrick, and A. Meeraus,Release 2.25 GAMS: A User's Guide, Boyd & Fraser, Danvers, MA, 1992.Google Scholar
  38. 38.
    M. Oral and O. Kettani, “A linearization procedure for quadratic and cubic mixed-integer problems,”Operations Research, Vol. 40, No. 1, pp. 109–116, 1992.MathSciNetCrossRefGoogle Scholar
  39. 39.
    F. Rose, T. Steeves, and T. Carpenter, “VHDL performance modeling,”Proceedings 1st Annual RASSP Conference, Arlington, VA, Aug. 1994, pp. 60–70. URL: http://rassp.scra. org/public/confs/1st/papers.html#VHDL P.Google Scholar
  40. 40.
    C. Hein and D. Nasoff, “VHDL-based performance modeling and virtual prototyping,”Proceedings 1st Annual RASSP Conference, Arlington, VA, July 24–27, pp. 87–94, 1995. URL: Scholar
  41. 41.
    T. Steeves, F. Rose, T. Carpenter, J. Shackleton, and O. von der Hoff, “Evaluating distributed multiprocessor design,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 95–101. URL: Scholar
  42. 42.
    H. Commissariat, F. Gray, J. Armstrong, and G. Frank, “Developing re-usable performance models for rapid evaluation of computer architectures running DSP algorithms,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 103–108. URL: http://rassp. Scholar
  43. 43.
    P.M. Athanas and A.L. Abbott, “Real-time image processing on a custom computing platform,”Computer, pp. 16–24, Feb., 1995.Google Scholar
  44. 44.
    V.K. Madisetti,VLSI Digital Signal Processors: An Introduction to Rapid Prototyping and Design Synthesis, IEEE Press, Piscataway, NJ, 1995.MATHGoogle Scholar
  45. 45.
    R.H. Paulson, “Kindling: A RASSP application case study,”Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 24–27, 1995, pp. 79–85. URL: http://rassp.scra. org/public/confs/2nd/papers.html.Google Scholar
  46. 46.
    Vahey Michael et al., “Real time IRST development using RASSP methodology and process,”Proceedings 2nd Annual RASSP Conference, July 24–27, 1995, pp. 45–51. URL: Scholar
  47. 47.
    T. Egolf, V. Madisetti, S. Famorzadeh, and P. Kalutkiewicz, “Experiences with VHDL models of COTS RISC processors in virtual prototyping for complex systems synthesis,”Proceedings of the VHDL International Users' Forum (VIUF), San Diego, Spring 1995.Google Scholar
  48. 48.
    E.A. Rundquist, “RASSP benchmark 1: Virtual prototyping of a synthetic aperture radar processor,”Proceedings 2nd Annual RASSP Conference, July 24–27, 1995, pp. 169–175. URL: Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • T. Egolf
    • 1
  • M. Pettigrew
    • 1
  • J. DeBardelaben
    • 1
  • R. Hezar
    • 1
  • S. Famorzadeh
    • 1
  • A. Kavipurapu
    • 1
  • M. Khan
    • 1
  • Lan-Rong Dung
    • 1
  • K. Balemarthy
    • 1
  • N. Desai
    • 1
  • V. Madisetti
    • 1
  1. 1.School of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlantaUSA

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