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VHDL-based rapid system prototyping

  • T. Egolf
  • M. Pettigrew
  • J. DeBardelaben
  • R. Hezar
  • S. Famorzadeh
  • A. Kavipurapu
  • M. Khan
  • Lan-Rong Dung
  • K. Balemarthy
  • N. Desai
  • V. Madisetti
Article

Abstract

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.

Keywords

Clock Cycle Virtual Prototype Inverse Discrete Cosine Transform Signal Processing System Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • T. Egolf
    • 1
  • M. Pettigrew
    • 1
  • J. DeBardelaben
    • 1
  • R. Hezar
    • 1
  • S. Famorzadeh
    • 1
  • A. Kavipurapu
    • 1
  • M. Khan
    • 1
  • Lan-Rong Dung
    • 1
  • K. Balemarthy
    • 1
  • N. Desai
    • 1
  • V. Madisetti
    • 1
  1. 1.School of Electrical and Computer EngineeringGeorgia Institute of TechnologyAtlantaUSA

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