Journal of Automated Reasoning

, Volume 10, Issue 1, pp 115–136 | Cite as

Simplification in a satisfiability checker for VLSI applications

  • Frank Vlach


INSTEP is a satisfiability checker designed for the original purpose of solving a specific target set of problems in the formal verification of VLSI circuits. These are real-world problems concerning a sequential circuit that is part of a commercial chip manufactured by Texas Instruments. The program has succeeded in solving these problems, which require satisfiability checking for combinational representations containing up to around 10 000 variables and a graphical representation of around 17 000 nodes. It has also been successfully applied to a number of standard benchmark problems in combinational circuit verification. Results on these benchmarks are overall competitive with those for the widely used method based onbinary decision diagrams, and for the first time demonstrate the solution in polynomial time of certain benchmarks involving combinational multipliers.

A central part of the INSTEP algorthim is simplification. Most simplifications that take place in previous tautology checkers consist of the replacement of a formula by a shorter formula that is logically equivalent. Most simplifications in INSTEP replace a formula by another formula which isnot logically equivalent, but such that satisfiability is nevertheless preserved. These new simplifications depend on the pattern of occurrence of one or more variables and particularly on theirpolarity.

The simplifications used by INSTEP rest on several new theorems in an area of propositional calculus (or Boolean algebra) which is crucial to the general theory of effective simplification of propositional formulas. The primary purpose of the present paper is to demonstrate these theorems and explain the simplifications that depend on them.

For the present paper we have tried INSTEP on the well-known pigeonhole problem. So far as we know INSTEP is the first implemented program to produce proofs of polynomial length for pigeonhole problems. It also produces these proofs in polynomial time.

Key words

Hardware verification satisfiability checker pigeonhole problem 


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Copyright information

© Kluwer Academic Publishers 1993

Authors and Affiliations

  • Frank Vlach
    • 1
  1. 1.Department of Computer ScienceUniversity of North TexasDentonU.S.A.

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