Abstract
In practice, finite state concurrent systems often exhibit considerable symmetry. We investigate techniques for reducing the complexity of temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. In the past, symmetry has been exploited in computing the set of reachable states of a system when the transition relation is represented explicitly [14, 11, 19]. However, this research did not consider arbitrary temporal properties or the complications that arise when BDDs are used in such procedures.
We have formalized what it means for a finite state system to be symmetric and described techniques for reducing such systems when the transition relation is given explicitly in terms of states or symbolically as a BDD. Moreover, we have identified an important class of temporal logic formulas that are preserved under this reduction. Our paper also investigates the complexity of various critical steps, like the computation of the orbit relation, which arise when symmetry is used in this type of verification. Finally, we have tested our ideas on a simple cache-coherency protocol based on the IEEE Futurebus + standard.
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References
M. Browne, E. Clarke, and O. Grumberg, “Characterizing finite Kripke structures in propositional temporal logic,”Theoretical Comput. Sci., Vol. 59, pp. 115–131, 1988.
R.E. Bryant, “Graph-based algorithms for boolean function manipulation,”IEEE Trans. Comput., Vol. C-35, No. 8, 1986.
J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, and J. Hwang, ‘Symbolic model checking: 1020 states and beyond,” inProc. 5th Ann. Symp. on Logic in Comput. Sci., IEEE Comp. Soc. Press, June 1990.
L. Claesen (Ed.),Proc. 11th Int. Symp. on Comput. Hardware Description Lang. and their Applications, North-Holland, Apr. 1993.
E.M. Clarke, E.A. Emerson, and A.P. Sistla, “Automatic verification of finite-state concurrent systems using temporal logic specifications,”ACM Trans. Prog. Lang. Syst., Vol. 8, No. 2, pp. 244–263, 1986.
E.M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.L. McMillan, and L.A. Ness, “Verification of the Futurebus + cache coherence protocol,” to appear inProc. 11th Int. Symp. on Comput. Hardware Description Lang, and their Applications, Apr. 1993.
E.A. Emerson and A.P. Sistla, “Symmetry and model checking,” inProc. Fifth Workshop on Comput.-Aided Verification, C. Courcabetis (Ed.), June 1993.
E. Felt, G. York, R. Brayton, and A.S. Vincentelli, “Dynamic variable reordering for bdd minimiation,” inProc. EuroDAC, pp. 130–135, Sept. 1993.
M. Furst, J. Hopcroft, and E. Luks, “Polynomial-time algorithms for permutations groups,” inProc. 21st Ann. Symp. on Found. of Comput. Sci., 1980.
M. Garey and D. Johnson,Computers and Intractibility, W.H. Freeman and Company, 1979.
P. Huber, A. Jensen, L. Jepsen, and K. Jensen, “Towards reachability trees for high-level Petri nets,” inAdvances on Petri Nets, G. Rozenberg (Ed.), pp. 215–233, 1984.
S.L. Hurst, D.M. Miller, and J.C. Muzio,Special Techniques in Digital Logic, Academic Press, Inc., 1985.
IEEE Computer Society,IEEE Standard for Futurebus +—Logical Protocol Specification, Mar. 1992. IEEE Standard 896.I-1991.
C. Ip and D. Dill, “Better verification through symmetry,” to appear inProc. 11th Int. Symp. on Compuct. Hardware Description Lang. and their Applications, Apr. 1993.
R.P. Kurshan, “Testing containment of ω-regular languages,” Technical Report 1121-861010-33-TM, Bell Laboratories, 1986.
B. Lin and A.R. Newton, “Efficient symbolic manipulation of equivalence relations and classes,” inProc. 1991 Int. Workshop on Format Methods in VLSI Design, Jan. 1991.
K.L. McMillan and J. Schwalbe, “Formal verification of the Gigamax cache consistency protocol,” inShared Memory Multiprocessing, N. Suzuki (Ed.), MIT Press, 1992.
R. Rudell, “Dynamic variable reordering for ordered binary decision diagrams,” inProc. IEEE ICCAD, pp. 42–47, Nov. 1993.
P. Starke, “Reachability analysis of petri nets using symmetries,”Syst. Anal. Model. Simul., Vol. 8, Nos. 4/5, pp. 293–303, 1991.
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This research was sponsored in part by the Avionics Laboratory, Wright Research and Development Center, Aeronautical Systems Division (AFSC), U.S. Air Force, Wright-Patterson AFB, Ohio 45433-6543 under Contract F33615-90-C-1465, ARPA Order No. 7597 and in part by the National Science Foundation under Grant No. CCR-8722633 and in part by the Semiconductor Research Corporation under Contract 92-DJ-294.
The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government.
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Clarke, E.M., Enders, R., Filkorn, T. et al. Exploiting symmetry in temporal logic model checking. Form Method Syst Des 9, 77–104 (1996). https://doi.org/10.1007/BF00625969
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DOI: https://doi.org/10.1007/BF00625969