Formal Methods in System Design

, Volume 9, Issue 1–2, pp 77–104 | Cite as

Exploiting symmetry in temporal logic model checking

  • E. M. Clarke
  • R. Enders
  • T. Filkorn
  • S. Jha


In practice, finite state concurrent systems often exhibit considerable symmetry. We investigate techniques for reducing the complexity of temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. In the past, symmetry has been exploited in computing the set of reachable states of a system when the transition relation is represented explicitly [14, 11, 19]. However, this research did not consider arbitrary temporal properties or the complications that arise when BDDs are used in such procedures.

We have formalized what it means for a finite state system to be symmetric and described techniques for reducing such systems when the transition relation is given explicitly in terms of states or symbolically as a BDD. Moreover, we have identified an important class of temporal logic formulas that are preserved under this reduction. Our paper also investigates the complexity of various critical steps, like the computation of the orbit relation, which arise when symmetry is used in this type of verification. Finally, we have tested our ideas on a simple cache-coherency protocol based on the IEEE Futurebus + standard.


model checking symmetry temporal-logic 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    M. Browne, E. Clarke, and O. Grumberg, “Characterizing finite Kripke structures in propositional temporal logic,”Theoretical Comput. Sci., Vol. 59, pp. 115–131, 1988.Google Scholar
  2. 2.
    R.E. Bryant, “Graph-based algorithms for boolean function manipulation,”IEEE Trans. Comput., Vol. C-35, No. 8, 1986.Google Scholar
  3. 3.
    J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, and J. Hwang, ‘Symbolic model checking: 1020 states and beyond,” inProc. 5th Ann. Symp. on Logic in Comput. Sci., IEEE Comp. Soc. Press, June 1990.Google Scholar
  4. 4.
    L. Claesen (Ed.),Proc. 11th Int. Symp. on Comput. Hardware Description Lang. and their Applications, North-Holland, Apr. 1993.Google Scholar
  5. 5.
    E.M. Clarke, E.A. Emerson, and A.P. Sistla, “Automatic verification of finite-state concurrent systems using temporal logic specifications,”ACM Trans. Prog. Lang. Syst., Vol. 8, No. 2, pp. 244–263, 1986.Google Scholar
  6. 6.
    E.M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.L. McMillan, and L.A. Ness, “Verification of the Futurebus + cache coherence protocol,” to appear inProc. 11th Int. Symp. on Comput. Hardware Description Lang, and their Applications, Apr. 1993.Google Scholar
  7. 7.
    E.A. Emerson and A.P. Sistla, “Symmetry and model checking,” inProc. Fifth Workshop on Comput.-Aided Verification, C. Courcabetis (Ed.), June 1993.Google Scholar
  8. 8.
    E. Felt, G. York, R. Brayton, and A.S. Vincentelli, “Dynamic variable reordering for bdd minimiation,” inProc. EuroDAC, pp. 130–135, Sept. 1993.Google Scholar
  9. 9.
    M. Furst, J. Hopcroft, and E. Luks, “Polynomial-time algorithms for permutations groups,” inProc. 21st Ann. Symp. on Found. of Comput. Sci., 1980.Google Scholar
  10. 10.
    M. Garey and D. Johnson,Computers and Intractibility, W.H. Freeman and Company, 1979.Google Scholar
  11. 11.
    P. Huber, A. Jensen, L. Jepsen, and K. Jensen, “Towards reachability trees for high-level Petri nets,” inAdvances on Petri Nets, G. Rozenberg (Ed.), pp. 215–233, 1984.Google Scholar
  12. 12.
    S.L. Hurst, D.M. Miller, and J.C. Muzio,Special Techniques in Digital Logic, Academic Press, Inc., 1985.Google Scholar
  13. 13.
    IEEE Computer Society,IEEE Standard for Futurebus +—Logical Protocol Specification, Mar. 1992. IEEE Standard 896.I-1991.Google Scholar
  14. 14.
    C. Ip and D. Dill, “Better verification through symmetry,” to appear inProc. 11th Int. Symp. on Compuct. Hardware Description Lang. and their Applications, Apr. 1993.Google Scholar
  15. 15.
    R.P. Kurshan, “Testing containment of ω-regular languages,” Technical Report 1121-861010-33-TM, Bell Laboratories, 1986.Google Scholar
  16. 16.
    B. Lin and A.R. Newton, “Efficient symbolic manipulation of equivalence relations and classes,” inProc. 1991 Int. Workshop on Format Methods in VLSI Design, Jan. 1991.Google Scholar
  17. 17.
    K.L. McMillan and J. Schwalbe, “Formal verification of the Gigamax cache consistency protocol,” inShared Memory Multiprocessing, N. Suzuki (Ed.), MIT Press, 1992.Google Scholar
  18. 18.
    R. Rudell, “Dynamic variable reordering for ordered binary decision diagrams,” inProc. IEEE ICCAD, pp. 42–47, Nov. 1993.Google Scholar
  19. 19.
    P. Starke, “Reachability analysis of petri nets using symmetries,”Syst. Anal. Model. Simul., Vol. 8, Nos. 4/5, pp. 293–303, 1991.Google Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • E. M. Clarke
    • 1
  • R. Enders
    • 2
  • T. Filkorn
    • 2
  • S. Jha
    • 3
  1. 1.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA
  2. 2.Corporate Research and DevelopmentSiemens AGMuenchen 83Germany
  3. 3.School of Computer ScienceCarnegie Mellon UniversityPittsburghUSA

Personalised recommendations