Abstract
One of the prime considerations for high scalar performance in supercomputers is a low memory latency. With the increasing disparity between main memory and CPU clock speeds, the use of an intermediate memory in the hierarchy becomes necessary. In this paper, we present an intermediate memory structure called a programmable cache. A programmable cache exploits structural locality to decrease the average memory access time. We evaluate the concept of a programmable cache by using the vector registers in the CRAY X-MP and Y-MP supercomputers as a programmable cache. Our results indicate that a programmable cache can be used profitably to reduce the memory latency if the pattern of references to a data structure can be determined at compile time.
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The work of the first author was supported in part by NSF Grant CCR-8706722.
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Sohi, G.S., Hsu, WC. The use of intermediate memories for low-latency memory access in supercomputer scalar units. J Supercomput 4, 5–21 (1990). https://doi.org/10.1007/BF00162340
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DOI: https://doi.org/10.1007/BF00162340