Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance
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An optimally designed Dual Source Vertical Tunnel Field Effect Transistors is proposed and investigated using technology computer aided design simulation. The vertical tunnel FET have dispersal of source channel drain in the vertical direction which will enhance the scalability of the simulated device. The benefit of the TFET is switching mechanism which is done by quantum tunnelling method through a barrier instead of thermionic emission over the barrier as that of conventional MOSFETs. The key of this paper, we have developed two-dimensional model of single drain with dual source n-type vertical tunnel field effect transistor. Further introduction to an ultra-thin channel among the drain and gate region will makes aggressive improvement in the numerical simulations of minimum threshold voltage (VT) of 0.15 V and average subthreshold slope of 3.47 mV/decade. The variation effect in the channel thickness, source height, drain doping, source doping, temperature and work function has been simulated and examined by 2D silvaco TCAD tool. High ON current and low OFF current is recorded as 1.74 × 10−4 A/µm and 6.92 × 10−13 A/µm respectively with ION/IOFF current ratio in order of 108 to 109.
KeywordsDual source vertical tunnel FET (DSV-TFET) Subthreshold slope (SS) Band-2-band tunneling (B2BT) Work function (WF) Average subthreshold slope (AVSS) Low power (LP)
We thank the VLSI design group of NIT Jalandhar for their interest in this work and useful comments to draft the final form of the paper. The support of DST-SERB Project (ECR/2017/000922) is gratefully acknowledged. We would like to thank NIT Jalandhar for lab facilities and research environment to carry out this work.
- 1.D. Kahng, U.S. Patent No. 3,102,230 (1963)Google Scholar
- 3.G.E. Moore, Proc. IEEE 11, 33 (2006)Google Scholar
- 6.C. Bulucea, F.-C. Wang, P. Chaparala, U.S. Patent No. 6, 548, 842 (2003)Google Scholar
- 9.K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, Digest. International Electron Devices Meeting, IEEE 7509297 (2002)Google Scholar
- 14.B. Hoefflinger, Int. Roadmap Semicond. 2, 143 (2016)Google Scholar
- 15.M. Neisser, S. Wurm, Adv. Opt. Technol. 4, 235 (2015)Google Scholar
- 20.W. Girish, R. Balwinder, J. Electron. Mater. 47, 4883 (2018)Google Scholar
- 23.S. Singh, B. Raj, in First International Conference on Secure Cyber Computing and Communication, 192 (2018)Google Scholar