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A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

  • Fahimeh Danehdaran
  • Shaahin Angizi
  • Milad Bagherian Khosroshahy
  • Keivan NaviEmail author
  • Nader Bagherzadeh
Original Research
  • 6 Downloads

Abstract

Nowadays, arithmetic computing is an important subject in computer architectures in which the one-bit full-adder gate plays a significant role. Thus, efficient design of such full-adder component can be beneficial to the overall efficiency of the entire system. In this essay, a novel method for the design and simulation of a combined majority gate toward realization of the one-bit full-adder gate is proposed. We inspect an alternative approach for the streamlined physical design of quantum-dot cellular automata (QCA) full-adder circuits in which the placement of input cells and wire crossing congestion are substantially reduced. The proposed method has outstanding characteristics such as low complexity, reduced area consumption, simplified physical design, and ultra-high speed one-bit full-adder. Based on simulation results the proposed design provides 33.33% reduction in area and 20.00% improvement in complexity as well as 10.49% in 1 Ek reduction in power consumption.

Keywords

Quantum-dot cellular automata (QCA) Combined majority gate Full-adder gate Power consumption Arithmetic circuit 

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Copyright information

© Bharati Vidyapeeth's Institute of Computer Applications and Management 2019

Authors and Affiliations

  1. 1.School of Computer ScienceInstitute for Research in Fundamental Sciences (IPM)TehranIran
  2. 2.Department of Electrical and Computer EngineeringUniversity of Central FloridaOrlandoUSA
  3. 3.Department of Computer Science and EngineeringShahid Beheshti University, G.CTehranIran
  4. 4.Department of Electrical Engineering and Computer ScienceUniversity of CaliforniaIrvineUSA

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