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Journal of Hardware and Systems Security

, Volume 2, Issue 4, pp 322–332 | Cite as

Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

  • Raul Quijada
  • Roger Dura
  • Jofre PallaresEmail author
  • Xavier Formatje
  • Salvador Hidalgo
  • Francisco Serra-Graells
Article
  • 244 Downloads

Abstract

A high degree of automation is required when facing full-IC reverse engineering. In this paper, we present a methodology to delayer the chip, acquire SEM images of each layer, obtain the three-dimensional layer reconstruction, and generate a vectorized file in GDSII format for further automatic netlist extraction. A custom software tool named GDS-X has been developed to perform all the required steps from image acquisition to the GDSII file generation. Applying a novel tile mosaicking strategy and using state-of-the-art machine learning techniques for image segmentation, this software reduces dramatically the time required to complete these procedures while minimizing errors compared to old manual reverse engineering techniques.

Keywords

Reverse engineering Chip delayering Mosaicking Machine learning 

Notes

Acknowledgements

The authors would like to thank the IMB-CNM clean room staff and specially the RIE, SEM image acquisition and carbon deposition teams for their valuable support and advice.

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Copyright information

© Springer Nature Switzerland AG 2018

Authors and Affiliations

  1. 1.Reverse Engineering Group, Instituto de Microelectronica de Barcelona IMB-CNM (CSIC); Carrer Tillers s/nBarcelonaSpain
  2. 2.Department of Microelectronics and Electronic SystemsUniversitat Autonoma de Barcelona, Edifici Q, Carrer de les SitgesCerdanyola del VallesSpain

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