Dynamic Foreground Calibration of Binary-Weighted Current-Steering DAC

  • Khalil MonfarediEmail author
  • Sara Jan Mohammadi
Research Paper


In this paper, a novel versatile calibration technique is proposed for current-steering binary-weighted DACs. This work is motivated by the fact that, in spite of the relative tendency to utilize the binary-weighted converters, there are very few calibration techniques dealing with their matching accuracy and transient performance. The introduced calibration technique can dynamically calibrate the DAC, in an arbitrary and repeated manner whenever needed. The system utilizes two clock pulses: the slow one for calibration and the other high-speed pulse for normal operation. The proposed calibration structure can strictly eliminate transistor mismatch-induced errors incorporating a unique calibration block utilized in an algorithmic manner for all current blocks. Implementing a configurable triple-path scheme, the current reference is updated by summing all of the adjusted LSB currents up, to calibrate the next upper MSB current. The transient behavior is improved due to the built-in intrinsic positive feedback-enabled deglitcher. Introducing tremendous overall current error as high as 125 LSB to the binary current blocks, the performance of the proposed calibration technique is validated for a 10-bit DAC by Cadence simulations utilizing TSMC 180-nm CMOS technology applying sampling frequency of 125 MHz for 1.8 V supply voltage and 500 nA LSB current.


Binary-weighted Current-steering DAC Dynamic foreground calibration Intrinsic positive feedback-enabled deglitcher Serial calibration 


  1. Azhari SJ, Monfaredi K, Amiri S (2012) A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV. Int Nano Lett 2:35CrossRefGoogle Scholar
  2. Chou F-T, Hung C-C (2016) Glitch energy reduction and SFDR enhancement techniques for low-power binary-weighted current-steering DAC. IEEE Trans Very Large Scale Integr (VLSI) Syst 24:2407–2411Google Scholar
  3. Darji PG, Parikh CD (2015) Novel analog calibration technique for current-steering DACs. Circuits Syst Signal Process 34:2407–2418CrossRefGoogle Scholar
  4. Darji PG, Parikh CD (2016) Novel analog calibration technique for current-steering DACs’ dynamic performance. Circuits Syst Signal Process 35:2616–2625CrossRefGoogle Scholar
  5. Deveugele J, Steyaert MS (2006) A 10-bit 250-MS/s binary-weighted current-steering DAC. IEEE J Solid State Circuits 41:320–329CrossRefGoogle Scholar
  6. Grasso AD, Mirabella CA, Pennisi S (2008) CMOS current-steering DAC architectures based on the triple-tail cell. Int J Circuit Theory Appl 36:233–246CrossRefGoogle Scholar
  7. Guo G, Wang Y, Su W, Jia S, Zhang G, Zhang X (2012) Binary tree structure random dynamic element matching technique in current-steering DACs. In: 2012 IEEE 11th international conference on solid-state and integrated circuit technology (ICSICT), pp 1–3Google Scholar
  8. Lee C-I, Lin W-C (2015) MOSFET channel resistance characterization from the triode region to impact ionization region with the inductive breakdown network. Microelectron Reliab 55:481–485CrossRefGoogle Scholar
  9. Lin W-T, Kuo T-H (2012) A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection. IEEE J Solid-State Circuits 47:444–453CrossRefGoogle Scholar
  10. McDonnell SM, Patel VJ, Duncan L, Dupaix B, Khalil W (2017) Compensation and calibration techniques for current-steering DACs. IEEE Circuits Syst Mag 17:4–26CrossRefGoogle Scholar
  11. Mohyar SN, Murakami M, Motozawa A, Kobayashi H, Kobayashi O, Matsuura T (2015) sfdr improvement algorithms for current-steering DACs. Key Eng Mater 643:101CrossRefGoogle Scholar
  12. Monfaredi K (2018) Distributed unique-size MOS technique: a promising universal approach capable of resolving circuit design bottlenecks of modern era. Circuits Syst Signal Process 1:21. CrossRefGoogle Scholar
  13. Monfaredi K, Baghtash HF, Azhari SJ (2012) A novel ultra-low-power low-voltage femto-ampere current mirror. Circuits Syst Signal Process 31:833–847CrossRefGoogle Scholar
  14. Myderrizi I, Zeki A (2009) A high-speed swing reduced driver suitable for current-steering digital-to-analog converters. In: European conference on circuit theory and design, 2009. ECCTD 2009, pp 635–638Google Scholar
  15. Pal N, Nandi P, Biswas R, Katakwar AG (2016) Placement-based nonlinearity reduction technique for differential current-steering DAC. IEEE Trans Very Large Scale Integr (VLSI) Syst 24:233–242CrossRefGoogle Scholar
  16. Pirkkalaniemi J, Waltari M, Kosunen M, Sumanen L, Halonen K (2003) A 14-bit current-steering DAC with current-mode deglitcher. Analog Integr Circuits Signal Process 35:33–45CrossRefGoogle Scholar
  17. Razavi B (1995) Principles of data conversion system design 126. IEEE press, New YorkGoogle Scholar
  18. Razavi B (2018) The current-steering dac [a circuit for all seasons]. IEEE Solid State Circuits Mag 10:11–15Google Scholar
  19. Saeedi S, Mehrmanesh S, Atarodi M (2005) A low voltage 14-bit self-calibrated CMOS DAC with enhanced dynamic linearity. Analog Integr Circuits Signal Process 43:137–145CrossRefGoogle Scholar
  20. Shen M-H, Tsai J-H, Huang P-C (2010) Random swapping dynamic element matching technique for glitch energy minimization in current-steering DAC. IEEE Trans Circuits Syst II Express Briefs 57:369–373CrossRefGoogle Scholar
  21. van Roermund A, Vertreg M, Leenaerts D, Briaire J, Doris K (2005) A 12b 500 MS/s DAC with > 70 dB SFDR up to 120 MHz in 0.18 μm CMOS. In: Solid-state circuits conference, 2005. Digest of technical papers. ISSCC. 2005 IEEE International, pp 116–588Google Scholar
  22. Weste NH, Harris D (2015) CMOS VLSI design: a circuits and systems perspective. Pearson Education India, NoidaGoogle Scholar
  23. Wu X, Palmers P, Steyaert MS (2008) A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC. IEEE J Solid State Circuits 43:2396–2403CrossRefGoogle Scholar
  24. Yi S-C (2012) An 8-bit current-steering digital to analog converter. AEU Int J Electron Commun 66:433–437CrossRefGoogle Scholar
  25. Yi S-C (2015) A 10-bit current-steering CMOS digital to analog converter. AEU Int J Electron Commun 69:14–17CrossRefGoogle Scholar

Copyright information

© Shiraz University 2019

Authors and Affiliations

  1. 1.Department of Electrical and Electronic Engineering, Engineering FacultyAzarbaijan Shahid Madani UniversityTabrizIran

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