Reliable S-Box Hardware Implementation by Gate-Level Fault Masking Enhancement

  • Saeide Sheikhpour
  • Ali MahaniEmail author
  • Nasour Bagheri


With technology scaling, fault tolerance has become more essential for digital circuits. Some solutions, like all types of redundancies, have been proposed to increase the reliability of the systems. In this paper, we present a cost-aware algorithm to enhance the fault tolerance ability of combinational digital circuits. Proposed algorithm improves the circuit logical masking with minimum area overhead based on an improved version of genetic algorithm (GA). Given a set of potential gates that are more sensitive to fault occurrence, we first extract feasible functional redundant, ffr, between the source nodes and the potential gates’ outputs that their improvement on logical masking be more than a pre-defined threshold and hold them in a library, Masking_Lib. Then, we have to find a set of minimum number of potential gates as a target to add appropriate ffr, so that the maximum improvement on logical masking with minimum area overhead is achieved. Since, finding a set of potential gates with their suitable ffrs to meet these objectives is an NP-hard problem, we formulize this, as an optimization problem and solve using GA. We introduce an efficient chromosome representation and an adaptive objective function along with the basic GA operators. Besides, we integrate an assimilation operator with GA in order to enhance its searching ability. Our approach is applied to composite field substitution box implementation (S-box) that forms the core building block of any hardware implementation of the Advanced Encryption Standard algorithm. The simulation and synthesis results have been reported to show the effectiveness of our approach. Through these results, it has been shown that our proposed algorithm provides reliable digital circuits based on different level of logical masking (from 25.58 to 52.15).


Logical masking AES S-box Fault tolerance 

List of Symbols

\( P \)

Potential gates set

\( \rho_{k} \)

kth potential gate


Source nodes set for ith potential gate


Feasible functional redundancy


Set of ffrs for kth potential gate


Logical masking

\( n_{\text{F}} \)

Number of faulty outputs

\( n_{i } \)

Number of primary inputs

\( n_{n} \)

Number of members of circuit netlist

\( T \)

Target gates set

\( \tau_{k} \)

kth target gate

\( n_{\tau } \)

Number of target gates

\( n_{\text{G,rg}} \)

Number of redundant gates

\( n_{\text{G,rg}}^{ \text{max} } \)

Upper limit of target gates

\( n_{\text{Tr,rg}} \)

Number of redundant transistors

\( n_{\text{Tr,rg}}^{ \text{max} } \)

Upper limit of redundant transistors


A pre-defined threshold


Number of injected faults


A sorted list of chromosomes


Percent of selected genes for assimilation


Percent of wealthy chromosomes among all


Percent of needy chromosomes among all


  1. Ahmad, N., Hasan, R., & Jubadi, W. M. (2010). Design of AES S-box using combinational logic optimization. In IEEE symposium on industrial electronics and applications (pp. 696–699). Scholar
  2. Ahmad, N., & Hasan, S. M. R. (2013). Low-power compact composite field AES S-box/Inv S-box design in 65 nm CMOS using novel XOR gate. Integration the VLSI Journal, 46(4), 333–344. Scholar
  3. Albayrak, G., & Albayrak, U. (2016). Investigation of ready mixed concrete transportation problem using linear programming and genetic algorithm. Civil Engineering Journal, 2(10), 491–496.Google Scholar
  4. Almukhaizim, S., & Makris, Y. (2008). Soft error mitigation through selective addition of functionally redundant wires. IEEE Transactions on Reliability, 57(1), 23–31. Scholar
  5. Ansari, M. S., Mahani, A., & Mohammadi, K. (2016). Low power modular redundancy: A power efficient fault tolerant approach for digital circuits. COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, 35(3), 1098–1106. Scholar
  6. Ban, T., & Naviner, L. (2011). Progressive module redundancy for fault-tolerant designs in nanoelectronics. Microelectronics Reliability, 51(9–11), 1489–1492. Scholar
  7. Chen, W., & Bazzi, A. M. (2017). Logic-based methods for intelligent fault diagnosis and recovery in power electronics. IEEE Transactions on Power Electronics, 32(7), 5573–5589. Scholar
  8. El-Maleh, A. H., & Oughali, F. C. (2014). A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits. Microelectronics Reliability, 54(1), 316–326. Scholar
  9. Flammini, F., Mazzocca, N., Vittorini, V., & Marrone, S. (2009). A new modeling approach to the safety evaluation of n-modular redundant computer systems in presence of imperfect maintenance. Reliability Engineering & System Safety (RESS), 94, 1422–1432. Scholar
  10. Gao, Y., Xiao, F., Liu, J., & Wang, R. (2015). Distributed soft fault detection for interval type-2 fuzzy-model-based stochastic systems with wireless sensor networks. IEEE Transactions on Industrial Informatics. Scholar
  11. Goldberg, D. E. (2006). Genetic algorithms. Delhi: Pearson Education India.Google Scholar
  12. Granado-Criado, J., Vega-Rodriguez, M., Sanchez-Perez, J., & Gomez-Pulido, J. (2010). A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integration the VLSI Journal, 43(1), 72–80. Scholar
  13. Hashemi, S. M., & Rahmani, I. (2018). Numerical comparison of the performance of genetic algorithm and particle swarm optimization in excavations. Civil Engineering Journal, 4(9), 2186–2196. Scholar
  14. Konaka, A., Coitb, D. W., & Smithc, A. E. (2006). Multi-objective optimization using genetic algorithms: A tutorial. Reliability Engineering & System Safety, 91(9), 992–1007. Scholar
  15. Koren, I., & Su, S. (1979). Reliability analysis of N-modular redundancy systems with intermittent and permanent faults. IEEE Transactions on Computer, 28(7), 514–520. Scholar
  16. Kotturi, D., Yoo, S.-M., & Blizzard, J. (2005). AES crypto chip utilizing high-speed parallel pipelined architecture. IEEE International Symposium on Circuits and Systems, 5, 4653–4656. Scholar
  17. Li, H., Gao, Y., Wu, L., & Lam, H. K. (2015). Fault detection for T-S fuzzy time-delay systems: Delta operator and input–output methods. IEEE Transactions on Cybernetics, 45(2), 229–241. Scholar
  18. Mahdavi, S. S., & Mohammadi, K. (2010). Reliability enhancement of digital combinational circuits based on evolutionary approach. Microelectronics Reliability, 50, 415–423. Scholar
  19. Morioka, S., & Satoh, A. (2002). An optimized S-box circuit architecture for low power AES design. In Proceedings of the international workshop cryptographic hardware and embedded systems (CHES ‘02) (pp. 172–186).
  20. Mozaffari-Kermani, M., & Reyhani-Masoleh, A. (2008). A lightweight concurrent fault detection scheme for the AES S-boxes using normal basis. In Proceedings of the international workshop cryptographic hardware and embedded systems (CHES ‘08) (pp. 113–129).
  21. Mozaffari-Kermani, M., & Reyhani-Masoleh, A. (2011). A lightweight high-performance fault detection scheme for the advanced encryption standard using composite field. IEEE Transactions on Very Large Scale Integration Systems, 19(1), 85–91. Scholar
  22. National Institute of Standards and Technologies. (2001). Announcing the Advanced Encryption Standard (AES) FIPS 197.Google Scholar
  23. Nicolaidis, M. (2005). Design for soft error mitigation. IEEE Transactions on Device and Materials Reliability, 5(3), 405–418. Scholar
  24. Pagliarini, S., dos Santos, G., Naviner, L. D. B., & Naviner, J.-F. (2012). Exploring the feasibility of selective hardening for combinational logic. Microelectronics Reliability, 52(9–10), 1843–1847. Scholar
  25. Saljoughi, A. S., Mehrvarz, M., & Mirvaziri, H. (2017). Attacks and intrusion detection in cloud computing using neural networks and particle swarm optimization algorithms. Emerging Science Journal, 1(4), 179–191. Scholar
  26. Sanchez-Clemente, A. J., Entrena, L., Hrbacek, R., & Sekanina, L. (2016). Error mitigation using approximate logic circuits: A comparison of probabilistic and evolutionary approaches. IEEE Transactions on Reliability, 65(4), 1871–1883. Scholar
  27. Sargolzaie, M. H. (2011). Low cost fault tolerant architecture for advanced encryption standard. Canadian Journal on Electrical and Electronics Engineering, 2(9), 427–432.Google Scholar
  28. Sheikh, A. T., & El-Maleh, A. (2017). An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing. Integration the VLSI Journal, 58, 35–46. Scholar
  29. Shojaei, M., & Mahani, A. (2016). A novel 2-phase reliability improvement of digital circuits. In AIP conference proceedings.
  30. Standaert, F. X., Rouvroy, G., Quisquater, J. J., & Legat, J. D. (2003). Efficient implementation of Rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs. In Proceedings of the international workshop cryptographic hardware and embedded systems (CHES ‘03) (pp. 334–350).
  31. Varzaneh, H. H., Neysiani, B. S., Ziafat, H., & Soltani, N. (2018). Recommendation systems based on association rule mining for a target object by evolutionary algorithms. Emerging Science Journal, 2(2), 100–107. Scholar
  32. Yao, R., Chen, Q. Q., Li, Z. W., et al. (2015). Multi-objective evolutionary design of selective triple modular redundancy systems against SEUs. Chinese Journal of Aeronautics, 28(3), 804–813. Scholar
  33. Zhang, X., & Parhi, K. K. (2004). High-speed VLSI architectures for the AES algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(9), 957–967. Scholar
  34. Zhou, B., Thambipillai, S., & Zhang, W. (2014). Soft error mitigation through selection of noninvert implication paths. In NASA/ESA conference on adaptive hardware and systems (AHS) (pp. 77–82).

Copyright information

© Brazilian Society for Automatics--SBA 2019

Authors and Affiliations

  1. 1.Department of Electrical EngineeringShahid Bahonar UniversityKermanIran
  2. 2.Department of Electrical EngineeringShahid Rajaee Teacher Training UniversityTehranIran

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