A modular approach for testable conservative reversible multiplexer circuit for nanoelectronic confine application
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Abstract
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any systemlevel design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nanoelectronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing stateofartworks, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.
Keywords
Quantum information science Reversible multiplexer Quantumdot cellular automata Quantum costIntroduction
The complementary metaloxide semiconductor (CMOS) circuit design in the nanometer scale range has primary limitations such as MOS transistor width (W), length (L) and short channel effect that cause degradation of the device performance [1]. To overcome the problems the research moved towards nanotechnology [2]. Recently quantumdot cellular automata (QCA) general theorems promise the principle of low power, high device density, high switching speed and high operating frequency (THz) [3]. On the other hand, reversible logic has a popular field in the area of digital logic that can perform computing with almost zero power consumption [4]. Energy dissipation is a significant factor in digital logic circuits. According to Landauer, the single bit of data lost generates KTln2 = 0.017 eV of heat energy, where K is Boltzmann’s constant and T = 300 K is the absolute temperature [5]. Bennett proved that a zero power dissipation in a digital circuit is likely only if the circuit is designed for reversible logic gates [6]. In low power area, the reversible logic technique has an emerging area in Nanoelectronics and quantum computing. In specific quantum, circuits are nanometric scale and high computation speed. Since they involve tiny size particle (known as qubits) and exist in the atomic scale level [7]. The advantage of reversible logic is that quantum computing is made of this method. Moreover, reversible logic is toplevel emerging technologies, which process highspeed computing, low power, and nanometric scale [8]. Initially, the conservative based circuits are designed that emphasis on controlling the fault, which in turn increase the reliability of the circuits [9]. The second most important factor is a cost, which basic part of the quantum cost. If we focus on these two points, then the efficiency of the circuit will be enhanced. The novelty of this work is to design the circuits by combining all the above two factors.
Among all digital integrated circuits, multiplexer circuits are the fundamental part, which is embedded in the module part of the control unit of the processor. More appropriately, the control unit of the processor consists of the multiplexer [9]. After reviewing the stateoftheart work in this area, it can be conceived that a significant amount of research has been done in this domain besides few works targets the conservative approach, combined quantum logic circuit, and QCA framework [4, 7, 10, 11, 12, 13, 14]. The circuit by the authors in [7] such as 2:1 multiplexer was presented by MXcqca gate using the conservative, but it is nonreversible. This multiplexer circuit has some constraints such as the modular approach cannot be developed for higherorder multiplexer, quantum circuit not realized because it is nonreversible. The main drawback of existing multiplexer in literature is it’s not conservative reversible logic based, many researchers synthesize effort for optimizing the QCA parameters such as cell count, area and latency as [jcel1, jcel2]. The tendency to use such nonconservative QCA multiplexer is not fault tolerance and its high error rate too [15, 16]. After reviewing all the stateofartwork, it can be analyzed that our proposed circuits have some speciality such as lowcost metric parameters (gate count, garbage outputs, and quantum cost) and conservative reversible logic based. In the more specific multiplexer, design approach extended for nbit input using the developed algorithm. Further QCA layout implementation of proposed multiplexer has been constructed which appropriate to current Nanoelectronics confine application.
Most of the above literature paper circuits discussed above not optimize, there is utilizing more quantum cost, not conservative approach and no quantum equivalent circuit of design. This means these designs are not costeffective in terms of quantum cost and it is not conservative. However, the introduced design of multiplexer achieve optimal value of parameters and the performance is also studied by expanding the quantum equivalent circuit for the proposed design.

We design a conservative, reversible m:1 type multiplexer using existing RCQCA gate. The presented quantum circuit shows the circuit is more costeffective regarding quantum cost as compared to existing ones.

We present the smaller QCA robust structure of multiplexer, and the simulation outcomes specify the correct functionality for the minimum clock cycle delay.

We design a costeffective, conservative reversible multiplexer based on proposed algorithm.

We design a 2:1 multiplexer layout through QCADesigner tool, which provide the 0.25 s latency and 0.24 µm^{2} area.

We synthesize the multiplexer based on algorithm it expand to n:1 multiplexer also and it helpful for ALU, and control unit of processor design.
The rest of the paper is organized as follows: “Basic terminologies” section discusses the basic terminologies related to our work. “Proposed multiplexer based on RCQCA gate” section discuss the proposed reversible gate RCQCA. The utility of RCQCA as a multiplexer is elaborated in “Existing conservative, reversible gates” section. Proposed gate cell layout is given in “Design of conservative reversible multiplexer gate in QCA” section. In “Table 4 presents the comparative analysis of multiplexer” section, the table presents the comparative analysis of multiplexer. Finally, a conclusion has been shown in section Conclusion.
Basic terminologies
This section, we have presented the basic terminology such as reversible logic, conservative, reversible logic and QCA that are related to this work. Basic terminologies have been reviewed in stateoftheart work as per [17, 18, 19, 20].
Definition 2.1
Definition 2.2
Definition 2.3
Definition 2.4
Definition 2.5
QCA has four clock zones; the utility is to control the information flow. Four clock zones are categories by four phase (Switch, Hold, release and relax). Clock zone is shown in Fig. 3e.
Definition 2.6
Proposed multiplexer based on RCQCA gate
To test the circuit, the conservative logic claims to have costefficient application in reversible logic circuits. In fact, the conservative feature is the prominent part of testing reversible gates [21]. Hence, to achieve a low error rate and testing feature, the conservative, reversible technique would truly be remarked as the useful feature for construction digital logic integrated circuits. The conservative, reversible logic useful in QCA technique since it addresses the costefficient concern, such as: reducing cell complexity, reducing delay, layout area, and power [14].
In this paper, a novel multiplexer, circuit have been constructed by existing reversible gate [21]. The RCQCA gate is utilized for the multiplexer circuit. In “Modular approaches to design a multiplexer” section, multiplexer circuits are presented.
Existing conservative, reversible gates
Modular approaches to design a multiplexer
4:1 Multiplexer data output
Select line inputs  Intermediate outputs  Data output  

Sel_{1}  Sel_{2}  X  Y  Out 
0  0  I _{0}  I _{2}  I _{2} 
0  1  I _{0}  I _{2}  I _{0} 
1  0  I _{1}  I _{3}  I _{3} 
1  1  I _{1}  I _{3}  I _{1} 
8:1 Multiplexer data output
Select line inputs  Intermediate outputs  Data output  

Sel_{1}  Sel_{2}  Sel_{3}  X  Y  Z  W  P  Q  Out 
0  0  0  I _{0}  I _{2}  Y  I _{4}  I _{6}  P  I _{2} 
0  0  1  I _{0}  I _{2}  Y  I _{4}  I _{6}  P  I _{6} 
0  1  0  I _{0}  I _{2}  X  I _{4}  I _{6}  W  I _{0} 
0  1  1  I _{0}  I _{2}  X  I _{4}  I _{6}  W  I _{4} 
1  0  0  I _{1}  I _{3}  Y  I _{5}  I _{7}  P  I _{3} 
1  0  1  I _{1}  I _{3}  Y  I _{5}  I _{7}  P  I _{7} 
1  1  0  I _{1}  I _{3}  X  I _{5}  I _{7}  W  I _{1} 
1  1  1  I _{1}  I _{3}  X  I _{5}  I _{7}  W  I _{5} 
Lemma 1
An m:1 multiplexer cascading link by the RCQCA can be synthesized by (m − 1) be the minimum gate count (GC) and constant input (CI), 2(m − 1) + \(\log_{2} m\) be the garbage output (GO) and 4(m − 1) quantum cost (QC)
Proof
Assume that the Eq. (8), (9) and (10) supports for m = n. Therefore, an m:1 multiplexer can be synthesized by (m − 1) gate count.
As a mathematical induction, the least 2(m − 1) + \(\log_{2} m\) garbage output for m:1 type of multiplexer.
Design of conservative reversible multiplexer gate in QCA
Lemma 2
The maximum latency required to synthesize a 2:1 multiplexer using simulation outcomes is 0.5.
Proof
In the 2:1 multiplexer, cell layout is depicted in Fig. 7. The outcomes are verified under the bistable approximation model with default parameters in QCA Designer. The simulation outcomes elucidate that when select input B = (0, 0) the outcomes P = (0, 1), appear after 0.5 latency i.e. input A = (0,1) is selected and sent to output node P. When to take the inputs B = (1, 1) the outcomes as P = (0, 1) i.e. input D = (0,1) is routed to output node P. Therefore, it is observe that ancilla inputs play an important role to get the output of multiplexer. Maximum latency of 2:1 multiplexer is 0.5, as depicted in simulation result in Fig. 8. Hence, maximum 0.5 latency is utilized for projects in 2:1 multiplexer.
Table 4 presents the comparative analysis of multiplexer
Performance metrics analysis of proposed multiplexer
Multiplexer  Metrics 

2:1  1 QC (RCQCA) = 6 
1 GO (RCQCA) = 4  
1 CI (RCQCA) = 1  
1 UD (RCQCA) = 1  
4:1  3 QC (RCQCA) = 3 × 6 = 18 
3 GO (RCQCA) = 2 + 3 + 3 = 8  
3 CI (RCQCA) = 1 + 1 + 1 = 3  
3 UD (RCQCA) = 3  
8:1  2 QC (4:1 mux) + 1 QC (RCQCA) = 2 × 18 + 6 = 42 
2 GO (4:1 mux) + 1 GO (RCQCA) = (6 + 8) + 3 = 17  
2 CI (4:1 mux) + 1 CI (RCQCA) = 2 × 3 + 1 = 7  
2 UD (RCQCA) = 2 × 3 + 1 = 7 
Comparative analysis results of multiplexer design in QCA
Comparison between the proposed and existing multiplexer
Type  [4]  [7]  [12]  [13]  Proposed  

2:1  GC  1  1  1  1  1 
GO  2  2  1  2  3  
QC  4  5  4  4  6  
Conservative  No  Yes  No  No  Yes  
Equivalent quantum circuit  No  No  No  No  Yes  
4:1  GC  3  3  3  6  3 
GO  5  5  5  10  8  
QC  12  15  12  28  12  
Conservative  No  Yes  No  No  Yes  
Equivalent quantum circuit  No  No  No  No  Yes  
m:1  GC  (m − 1)  3n  –  –  (m − 1) 
GO  (m − 1) + \(\log_{2} m\)  4m + 1  –  –  2(m − 1) + \(\log_{2} m\)  
QC  4(m − 1)  15m  –  –  4(m − 1)  
Conservative  No  Yes  –  –  Yes 
Conclusion
This work targets the basic factor such as costefficient solutions for nanoelectronics based confine application, which has been successfully presented in this article. The costefficient conservative reversible multiplexer has been discussed and introduced successfully. The synthesizer circuits discussed in this paper is new and has achieved the target results. In fact, we have explored our proposed reversible gate RCQCA in the dissimilar type of circuits such as multiplexer. First, the modular approach for multiplexer circuits, it presents better parameters as compared to existing ones. We have proven the reliability of multiplexer by lemmas. The inevitable optimal parameters m:1 mux is \(2\left( {m  1} \right) + \log_{2} m\) garbage outputs and 4(m − 1) quantum cost. The entire circuits work around RCQCA and its aim is to optimize the quantum cost. The RCQCA has only 6 quantum cost. Proposed multiplexer is analyzed on QCADesigner simulator. In further analysis has been included to determine the impact of RCQCA in QCA technology. It is found that 0.25 latency, 0.24 µm^{2} area, 177 cell complexity. The proposed dissimilar type of circuit will facilitate the coverage of low reversible parameters, QCA logic computing, and classification of QCA parameters such as complexity (cell count), speed (latency) and area usages.
Notes
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