High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion
Modular multiplication is a key operation in RSA cryptosystems. Modular multipliers can be realized using Montgomery algorithm. Montgomery algorithm employing carry save adders makes modular multiplication suitable and efficient. Montgomery modular multiplication can be carried out in two ways. All the operands are kept in carry save form in one of the ways. The input and output are kept in binary form, and intermediate operands are kept in carry save form in the other way which requires an efficient format converter. This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method. Format conversion is carried out through a format conversion unit which consists of a carry look-ahead unit and multiplexer unit. In addition, this multiplier merges two iterations, which reduces the number of clock cycles significantly. Merger of iteration requires integer multiples of inputs which is computed using the same format converter. Critical path delay of the multiplier is minimized by multiplying one of the inputs by four which simplifies necessary intermediate calculations. The total time required for one complete multiplication is significantly minimized due to reduction in required number of clock cycles with optimum critical path delay. Experimental results show that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.
KeywordsCarry save addition VLSI Modular exponentiation Montgomery modular multiplier Rivest, Shamir, and Adleman (RSA) cryptosystem
Authors are thankful to the project “Special Manpower Development Program for Chip to System Design (SMDP-C2SD)” sponsored by Ministry of Electronics and Information Technology (MeitY), Government of India, for providing technical facility.
- 3.Y.S. Kim, W.S. Kang, J.R. Choi, Implementation of 1024-bit modular processor for RSA cryptosystem, in Proceedings of Second IEEE Asia Pacific Conference on ASICs (2000), pp. 187–190Google Scholar
- 4.V. Bunimov, M. Schimmler, B. Tolg, A complexity-effective version of Montgomery’s algorithm, in Proceedings of the Workshop on Complexity Effects Designs (2002), pp. 1–7Google Scholar
- 5.Z.B. Hu, R.M. A. Shboul, V.P. Shirochin, An efficient architecture of 1024-bits Cryptoprocessor for RSA cryptosystem based on modified Montgomery’s algorithm, in Proceedings of the Fourth IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems (2007), pp. 643–646Google Scholar
- 8.K. Manochehri, S. Pourmozafari, Fast Montgomery modular multiplication by pipelined CSA architecture, in Proceedings of the IEEE International Conference on Microelectronics (2004), pp. 144–147Google Scholar
- 10.K. Manochehri, S. Pourmozafari, Modified radix-2 montgomery modular multiplication to make it faster and simpler. Proc. IEEE Int. Conf. Inf. Technol. 1, 598–602 (2005)Google Scholar
- 13.J.C. Neto, A.F. Tenca, W.V. Ruggiero, A parallel k-partition method to perform Montgomery multiplication, in Proceedings of the IEEE International Conference on Application-Specific Systems, Architecture Processors (2011), pp. 251–254Google Scholar
- 15.G. Sassaw, C.J. Jimenez, M. Valencia, High radix implementation of Montgomery multipliers with CSA, in Proceedings of the International Conference on Microelectronic (2010), pp. 315–318Google Scholar
- 17.S.-H. Wang, W.-C. Lin, J.-H. Ye, M.-D. Shieh, Fast scalable radix-4 Montgomery modular multiplier, in Proceedings of IEEE International Symposium on Circuits and Systems (2012), pp. 3049–3052Google Scholar
- 18.F. Gang, Design of modular multiplier based on improved montgomery algorithm and systolic array. Proc First Int. Multi-Symp. Comput. Comput. Sci. 2, 356–359 (2006)Google Scholar
- 19.G. Perin, D.G. Mesquita, F.L. Herrmann, J.B. Martins, Montgomery modular multiplication on reconfigurable hardware: fully systolic array vs parallel implementation, in Proceedings of the 6th Southern Programmable Logic Conference (2010), pp. 61–66Google Scholar
- 21.F. Vahid, Digital Design (Wiley, London, 2006), pp. 296–316Google Scholar