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Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating

  • T. ThamaraimanalanEmail author
  • P. Sampath
Short Communication
  • 6 Downloads

Abstract

Among various available techniques, power gating is a well-known method which is widely employed to minimize the leakage power in CMOS design. This paper proposes a delay-based power gating technique to minimize the leakage power in adders and multipliers. The proposed technique is verified using both fine-grain and coarse-grain power gating methodology. To validate the efficiency of the proposed method, the experimental analysis has been carried out in terms of leakage power and area. The results obtained from the experimental analysis indicate that the proposed method achieves 14.33% improvement in fine-grained power gating and 5.47% improvement in coarse-grained power gating in terms of average leakage power dissipation when compared with conventional power gating technique.

Keywords

Coarse-grain power gating Delay Fine-grain power gating Leakage power 

Notes

References

  1. 1.
    Kandasamy N, Ahmad F, Reddy S, Ramesh Babu M, Telagam N, Utlapalli S (2018) Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology. Microprocess Microsyst 59:15–28.  https://doi.org/10.1016/j.micpro.2018.03.003 CrossRefGoogle Scholar
  2. 2.
    Henzler S (2007) Power gating. Power management of digital circuits in deep sub-micron CMOS technologies advanced microelectronics. Springer, Dordrecht, pp 69–167.  https://doi.org/10.1007/1-4020-5081-x_5 CrossRefGoogle Scholar
  3. 3.
    Xu H, Vemuri R, Jone W-B (2011) Dynamic characteristics of power gating during mode transition. IEEE Trans Very Large Scale Integr Syst 19(2):237–249.  https://doi.org/10.1109/tvlsi.2009.2033699 CrossRefGoogle Scholar
  4. 4.
    Mutoh S, Douseki T, Matsuya Y, Aoki T, Yamada J (1995) 1 V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS. In: Sixth annual IEEE international ASIC conference and exhibit, pp 847–854.  https://doi.org/10.1109/asic.1993.410836
  5. 5.
    Priya M, Baskaran K, Krishnaveni D (2012) Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Eng 30:1163–1170.  https://doi.org/10.1016/j.proeng.2012.01.976 CrossRefGoogle Scholar
  6. 6.
    Thamaraimanalan T, Sampath P (2019) A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems. Cogn Syst Res 57:236–245.  https://doi.org/10.1016/j.cogsys.2018.10.033 CrossRefGoogle Scholar
  7. 7.
    Sjalander M, Drazdziulis M, Larsson-Edefors P, Eriksson H (2005) A low-leakage twin-precision multiplier using reconfigurable power gating. IEEE international symposium on circuits and systems.  https://doi.org/10.1109/iscas.2005.1464922
  8. 8.
    Weste NHE, Harris DM (2015) CMOS VLSI design: a circuits and systems perspective. Pearson, NoidaGoogle Scholar

Copyright information

© The National Academy of Sciences, India 2019

Authors and Affiliations

  1. 1.Department of ECESri Eshwar College of EngineeringCoimbatoreIndia
  2. 2.Department of ECEBannari Amman Institute of TechnologySathyamangalamIndia

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