Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study
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In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.
KeywordsParasitic suppression 2D smart power ICs Deep trench isolation 0.35 µm BiCMOS TCAD
The authors are thankful to the UpM (Union pour la Méditerranéenne) for the collaboration and joint research work.
- 5.Gupta S, Beckman JC, Kosier SL (2001) Unbiased guard ring for latchup-resistant, junction-isolated smart-power ICs. In: IEEE Proc BCTM, pp 188–191Google Scholar
- 6.Parthasarathy V, Zhu R, Khemka V, Roggenbauer T, Bose A, Hui P, Rodriquez P, Nivison J, Collins D, Wu Z, Puchades I, Butner M (2002) A 0.25 µm CMOS based 70 V smart power technology with deep trench for high- voltage isolation. In: Proc. IEDM, pp 459–462Google Scholar
- 7.Ferrari R, Morelli NM (1991) New levels of integration in automotive electronics. In: International symposium on vehicle electronics integration, pp 187–201Google Scholar
- 8.Wolf S (2002) Silicon processing for the VLSI era. Lattice Press, Sunset BeachGoogle Scholar
- 9.Berberich SE, Bauer AJ, Frey L, Ryssell H (2003) Trench sidewall doping for lateral power devices. In: IEEE proc of ESSDERC, pp 379–382Google Scholar