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Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

  • Mohamed AbouelattaEmail author
  • Marwa S. Salem
  • Ahmed Shaker
  • Mohamed Elbanna
  • Abdelhalim Zekry
  • Christian Gontrand
Short Communication
  • 44 Downloads

Abstract

In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT by using a P+ retardation implant region under the deep trench isolation region. The injection ratio of the parasitic BJT is reduced by a factor between 3 and 8.5. The effect of the trench length and the retardation implant is investigated using SENTAURUS TCAD simulations. It is confirmed, through using TCAD simulations, that the amount of the collected carriers of the sensitive devices changes as a function of the trench length and the presence of the retardation implant.

Keywords

Parasitic suppression 2D smart power ICs Deep trench isolation 0.35 µm BiCMOS TCAD 

Notes

Acknowledgements

The authors are thankful to the UpM (Union pour la Méditerranéenne) for the collaboration and joint research work.

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Copyright information

© The National Academy of Sciences, India 2019

Authors and Affiliations

  1. 1.Faculty of EngineeringAin Shams UniversityCairoEgypt
  2. 2.Computer CollegeHail UniversityHailSaudi Arabia
  3. 3.Modern Science and Arts University (MSA)CairoEgypt
  4. 4.INSA- LyonVilleurbanneFrance
  5. 5.IEPUniversité Euro-méditerranéenne de Fès, INSA- FèsFèsMorocco

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