Advertisement

National Academy Science Letters

, Volume 41, Issue 3, pp 147–150 | Cite as

An Improved Digital FIR Filter Design Using Fast FIR Algorithm and Modified Carry Save Addition

  • R. Mahalakshmi
  • T. Sasilatha
Short Communication
  • 60 Downloads

Abstract

Adders and multipliers are the two important arithmetic units in any form of digital filters. Though the adders and multipliers are the fundamental arithmetic units in digital FIR filters, the multipliers are more responsible for power consumption. In existing fast FIR algorithm based digital filters, the number of multipliers is reduced at the expense of adder circuits. This paper presents an arithmetic optimization of reconfigurable digital FIR filters using fast FIR algorithm and modified carry save addition to reduce the power consumption. The modified carry save addition is incorporated to efficiently combine the partial products of the multiplication process. The mathematical analysis reveals that significant amount of hardware savings can be achieved using the proposed design. The ASIC implementation using TSMC 65 nm technology shows that the proposed methodology occupies less area and consumes less power while comparing with conventional approach.

Keywords

Finite impulse response (FIR) filter Power consumption Modified carry save adder Application specific integrated circuit 

References

  1. 1.
    Tsao YC, Choi K (2012) Area-efficient VLSI implementation for parallel linear-phase FIR digital filters of odd length based on fast FIR algorithm. IEEE Trans Circuits Syst II: Express Briefs 59(6):371–375CrossRefGoogle Scholar
  2. 2.
    Chen PY, Van LD, Khoo IH, Reddy HC, Lin CT (2011) Power-efficient and cost-effective 2-D symmetry filter architectures. IEEE Trans Circuits Syst I: Regul Pap 58(1):112–125MathSciNetCrossRefGoogle Scholar
  3. 3.
    Gustafsson O (2007) A difference based adder graph heuristic for multiple constant multiplication problems. In: Proceedings of IEEE International Symposium on Circuits Systems pp 1097–1100Google Scholar
  4. 4.
    Chen KH, Chiueh TD (2006) A low-power digit-based reconfigurable FIR filter. IEEE Trans Circuits Syst II, Exp Briefs 53(8):617–621CrossRefGoogle Scholar
  5. 5.
    Mahesh R, Vinod AP (2010) New reconfigurable architectures for implementing filters with low complexity. IEEE Trans Comput Aided Des Integr Circuits Syst 29(2):275–288CrossRefGoogle Scholar
  6. 6.
    Yu Z, Yu ML, Azadet K, Wilson AN Jr, (2001) A low power FIR filter design technique using dynamic reduced signal representation. In: Proceedings of International Symposium on VLSI Technique Systems and Applications pp 113–116Google Scholar
  7. 7.
    Cheng C, Parhi KK (2004) Hardware efficient fast parallel FIR filter structures based on iterated short convolution. IEEE Trans Circuits Syst I Reg Pap 51(8):1492–1500MathSciNetCrossRefzbMATHGoogle Scholar
  8. 8.
    Cheng C, Parhi KK (2005) Furthur complexity reduction of parallel FIR filters. Proc IEEE ISCAS 2:1835–1838Google Scholar
  9. 9.
    Cheng C, Parhi KK (2007) Low-cost parallel FIR structures with 2-stage parallelism. IEEE Trans Circuits Syst I Reg Pap 54(2):280–290MathSciNetCrossRefzbMATHGoogle Scholar
  10. 10.
    Pothuri SM, Palsodkar P (2015) Area-reduced parallel FIR digital filter structures based on Modified Winograd Algorithm. In: 2015 international conference on IEEE communications and signal processing (ICCSP). pp 0588–0591Google Scholar
  11. 11.
    Mayilavelane A, Berscheid B (2016) A Fast FIR filtering technique for multirate filters. Integr VLSI J 52:62–70CrossRefGoogle Scholar
  12. 12.
    Chung JG, Parhi KK (2002) Frequency-spectrum-based low-area lowpower parallel FIR filter design. EURASIP J Appl Signal Process 9:444–453Google Scholar
  13. 13.
    Tsao YC, Choi K (2010) Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(2):366–371CrossRefGoogle Scholar
  14. 14.
    Ramkumar B, Kittur HM, MaheshKannan P (2010) ASIC implementation of modified faster carry save adder. Eur J Sci Res 42(1):53–58Google Scholar

Copyright information

© The National Academy of Sciences, India 2018

Authors and Affiliations

  1. 1.Saveetha Engineering CollegeChennaiIndia
  2. 2.S. A. Engineering CollegeChennaiIndia

Personalised recommendations