Advertisement

Journal of Cryptographic Engineering

, Volume 2, Issue 2, pp 91–97 | Cite as

Sequential multiplier with sub-linear gate complexity

  • M. Anwar Hasan
  • Christophe Negre
Regular Paper

Abstract

In this article, we present a new sequential multiplier for extended binary finite fields. Like its existing counterparts, the proposed multiplier has a linear complexity in flip-flop or temporary storage requirements, but a sub-linear complexity in gate counts. For the underlying polynomial multiplication, the proposed field multiplier relies on the Horner scheme.

Keywords

Binary polynomial multiplication Sequential multiplier Horner scheme Sub-linear gate complexity 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Daemen J., Rijmen V.: The Design of Rijndael: AES—The Advanced Encryption Standard. Springer, Verlag (2002)zbMATHGoogle Scholar
  2. 2.
    Fan H., Hasan M.A.: A new approach to sub-quadratic space complexity parallel multipliers for extended binary fields. IEEE Trans. Comput. 56(2), 224–233 (2007)MathSciNetCrossRefGoogle Scholar
  3. 3.
    Fan, H., Sun, J., Gu, M., Lam, K.-Y.: Overlap-free karatsuba-ofman polynomial multiplication algorithms. Cryptology ePrint Archive, Report 2007/393 (2007)Google Scholar
  4. 4.
    Guajardo G., Guneysu T., Paar C., Kumar S., Pelzl J.: Efficient hardware implementation of finite fields with applications to cryptography. Acta Applicandae Mathematicae 93(1–3), 75–118 (2006)MathSciNetzbMATHCrossRefGoogle Scholar
  5. 5.
    Hasan M.A., Wang M., Bhargava V.K.: A modified Massey-Omura parallel multiplier for a class of finite fields. IEEE Trans. Comput. 42(10), 1278–1280 (1993)zbMATHCrossRefGoogle Scholar
  6. 6.
    Koblitz N.: Elliptic curve cryptosystems. Math. Comput. 48, 203–209 (1987)MathSciNetzbMATHCrossRefGoogle Scholar
  7. 7.
    Leone, M.: A new low complexity parallel multiplier for a class of finite fields. In Proceedings of CHES’01, London, UK, pp. 160–170. Springer, Berlin (2001)Google Scholar
  8. 8.
    Mastrovito, E.: VLSI designs for multiplication over finite fields F (2m). In: 6th International Conference on Applied Algebra, Algebraic Algorithm and Error-Correcting Codes (AAECC-6), pp. 297–309 (1988)Google Scholar
  9. 9.
    Miller, V.: Use of elliptic curves in cryptography. In: Advances in Cryptology, proceeding’s of CRYPTO’85. LNCS, vol. 218, pp. 417–426. Springer, Berlin (1986)Google Scholar
  10. 10.
    Paar C.: A new architecture for a parallel finite field multiplier with low complexity based on composite fields. IEEE Trans. Comput. 45(7), 856–861 (1996)MathSciNetzbMATHCrossRefGoogle Scholar
  11. 11.
    Reyhani-Masoleh, A.: A new bit-serial architecture for field multiplication using polynomial bases. In: CHES 2008, pp. 300–314 (2008)Google Scholar
  12. 12.
    Song L., Parhi K.K.: Low-energy digit-serial/parallel finite field multipliers. J. VLSI Signal Process. Syst. 19(2), 149–166 (1998)CrossRefGoogle Scholar
  13. 13.
    Sunar B., Koc C.: Mastrovito multiplier for all trinomials. IEEE Trans. Comput. 48(5), 522–527 (1999)MathSciNetzbMATHCrossRefGoogle Scholar
  14. 14.
    Wang M., Blake I.F.: Bit serial multiplication in finite fields. SIAM J. Discret. Math. 3(1), 140–148 (1990)MathSciNetzbMATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag 2012

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of WaterlooWaterlooCanada
  2. 2.ECE DepartmentUniversity of WaterlooWaterlooCanada
  3. 3.LIRMM, Université Montpellier 2MontpellierFrance
  4. 4.Team DALIUniversité de PerpignanPerpignanFrance

Personalised recommendations