An on-chip glitchy-clock generator for testing fault injection attacks

  • Sho Endo
  • Takeshi Sugawara
  • Naofumi Homma
  • Takafumi Aoki
  • Akashi Satoh
Regular Paper


This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.


Fault injection attacks Clock glitch RSA Safe-error attack 


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Copyright information

© Springer-Verlag 2011

Authors and Affiliations

  • Sho Endo
    • 1
  • Takeshi Sugawara
    • 1
  • Naofumi Homma
    • 1
  • Takafumi Aoki
    • 1
  • Akashi Satoh
    • 2
  1. 1.Tohoku UniversitySendaiJapan
  2. 2.National Institute of Advanced Industrial Science and TechnologyTsukubaJapan

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