Journal of Cryptographic Engineering

, Volume 1, Issue 1, pp 37–55 | Cite as

Utilizing hard cores of modern FPGA devices for high-performance cryptography

Regular Paper

Abstract

This article presents a unique design approach for the implementation of standardized symmetric and asymmetric cryptosystems on modern FPGA devices. In contrast to many other FPGA implementations that algorithmically optimize the cryptosystems for being optimally placed in the generic array logic, our primary implementation goal is to shift as many cryptographic operations as possible into specific hard cores that have become available on many reconfigurable devices. For example, some of these dedicated functions are designed to provide large blocks of memory or fast arithmetic functions for Digital Signal Processing applications that can also be adopted for efficient cryptographic implementations. Based on these dedicated functions, we present specific design approaches that enable a performance for the symmetric AES block cipher (FIPS 197) of up to 55 GBit/s and a throughput of more than 30.000 scalar multiplications per second for asymmetric Elliptic Curve Cryptography over NIST’s P-224 prime (FIPS 186-3).

Keywords

FPGA implementations Function hard cores High-performance AES ECC 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Algotronix Ltd.: AES G3 Data Sheet: Xilinx Edition, October 2007. Available at http://www.algotronix-store.com/kb_results.asp?ID=7
  2. 2.
    ANSI X9.62-2005.: American National Standard X9.62: The Elliptic Curve Digital Signature Algorithm (ECDSA) (2005)Google Scholar
  3. 3.
    Avanzi R.M., Cohen H., Doche C., Frey G., Lange T., Nguyen K., Vercauteren F.: Handbook of Elliptic and Hyperelliptic Curve Cryptography. Chapman and Hall/CRC, Boca Raton (2005)Google Scholar
  4. 4.
    Blum T., Paar C.: High radix montgomery modular exponentiation on reconfigurable hardware. IEEE Trans. Comput. 50(7), 759–764 (2001)CrossRefGoogle Scholar
  5. 5.
    Bulens P., Standaert F., Quisquater J.-J., Pellegrin P., Rouvroy G.: Implementation of the AES-128 on Virtex-5 FPGAs. In: Vaudenay, S. (ed.) Proceedings of First International Conference on Cryptology in Africa—AFRICACRYPT 2008. LNCS Series, vol. 5023, pp. 16–26. Springer, Berlin (2008)Google Scholar
  6. 6.
    Chaves, R., Kuzmanov, G., Vassiliadis, S., Sousa, L.: Reconfigurable memory-based AES co-processor. In: Proceedings of the Workshop on Reconfigurable Architectures (RAW 2006), p. 192 (2006)Google Scholar
  7. 7.
    Chodowiec P., Gaj K.: Very compact FPGA Implementation of the AES algorithm. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS, vol. 2779, pp. 319–333. Springer, Berlin (2003)CrossRefGoogle Scholar
  8. 8.
    Comba P.G.: Exponentiation cryptosystems on the IBM PC. IBM Syst. J. 29(4), 526–538 (1990)CrossRefGoogle Scholar
  9. 9.
    Daemen J., Rijmen V.: The design of Rijndael: AES—the advanced encryption standard. Springer, Berlin (2002)MATHGoogle Scholar
  10. 10.
    Daly A., Marnane W., Kerins T., Popovici E.: An FPGA Implementation of a GF(p) ALU for encryption processors. Elsevier—Microprocess. Microsyst. 28(5–6), 253–260 (2004)CrossRefGoogle Scholar
  11. 11.
    de Dormale G.M., Quisquater J.-J.: High-speed hardware implementations of Elliptic Curve Cryptography: a survey. J. Syst. Archit. 53(2–3), 72–84 (2007)Google Scholar
  12. 12.
    Diffie W., Hellman M.: New directions in cryptography. IEEE Trans. Inform. Theory 22, 644–654 (1976)CrossRefMATHMathSciNetGoogle Scholar
  13. 13.
    Drimer, S., Güneysu, T., Paar, C.: DSPs, BRAMs and a pinch of logic: new recipes for AES on FPGAs. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 99–108. IEEE Computer Society, April 2008. Source code available at: http://www.cl.cam.ac.uk/~sd410/aes/
  14. 14.
    Eberle, H., Gura, N., Chang-Shantz, S.: A cryptographic processor for arbitrary elliptic curves over GF(2m). In: Application-Specific Systems, Architectures, and Processors (ASAP), pp. 444–454 (2003)Google Scholar
  15. 15.
    ECRYPT. eBATS.: ECRYPT Benchmarking of Asymmetric Systems, March 2007. Available at http://www.ecrypt.eu.org/ebats/
  16. 16.
    Elbirt A.J., Yip W., Chetwynd B., Paar C.: An FPGA-based Performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 9(4), 545–557 (2001)CrossRefGoogle Scholar
  17. 17.
    Elgamal T.: A public key cryptosystem and a signature scheme based on discrete logarithms. IEEE Trans. Inform. Theory 31(4), 469–472 (1985)CrossRefMATHMathSciNetGoogle Scholar
  18. 18.
    Fischer V., Drutarovský M.: Two methods of Rijndael implementation in reconfigurable hardware. In: Koç, Ç.K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162, pp. 77–92. Springer, Berlin (2001)CrossRefGoogle Scholar
  19. 19.
    Gaudry, P., Thomé, E.: The \({{\sf mp}\mathbb{F}q}\) Library and implementing Curve-based Key Exchanges. Workshop on Software Performance Enhancement for Encryption and Decryption (SPEED 2007) (2007)Google Scholar
  20. 20.
    Good T., Benaissa M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), LNCS, vol. 3659, pp. 427–440. Springer, Berlin (2005)CrossRefGoogle Scholar
  21. 21.
    Güneysu T., Paar C.: Ultra high performance ECC over NIST primes on commercial FPGAs. In: Oswald, E., Rohatgi, P. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008). LNCS, vol. 5154., pp. 62–78. Springer, Berlin (2008)CrossRefGoogle Scholar
  22. 22.
    Hamilton, M., Marnane, W.P.: FPGA implementation of an Elliptic Curve Processor Using the GLV method. In: Proceedings of International Conference Reconfigurable Computing and FPGAs ReConFig ’09, pp. 249–254 (2009)Google Scholar
  23. 23.
    Hankerson D.R., Menezes A.J., Vanstone S.A.: Guide to Elliptic Curve Cryptography. Springer, New York (2004)MATHGoogle Scholar
  24. 24.
    Helion Technology: High Performance AES (Rijndael) Cores for Xilinx FPGAs (2007). http://www.heliontech.com/downloads/aes_xilinx_helioncore.pdf
  25. 25.
    Hodjat, A., Verbauwhede, I.: A 21.54 Gbits/s fully pipelined AES processor on FPGA. In: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), pp. 308–309. IEEE Computer Society (2004)Google Scholar
  26. 26.
    Ichikawa, T., Kasuya, T., Matsui, M.: Hardware evaluation of the AES finalists. AES Candidate Conference, pp. 13–14 (2000)Google Scholar
  27. 27.
    Järvinen, K.U.: Studies on high-speed hardware implementations of cryptographic algorithms. PhD thesis, Helsinki University of Technology (2008)Google Scholar
  28. 28.
    Järvinen, K.U., Tommiska, M.T., Skyttä, J.O.: A Fully Pipelined Memoryless 17.8 Gbps AES-128 Encryptor. In: Proceedings of the International Symposium on Field Programmable Gate Arrays (FPGA 2003), pp. 207–215. ACM Press, New York (2003)Google Scholar
  29. 29.
    Karatsuba A., Ofman Y.: Multiplication of multidigit numbers on automata. Sov. Phys.—Doklady 7(7), 595–596 (1963)Google Scholar
  30. 30.
    McIvor, C., McLoone, M., McCanny, J.: An FPGA Elliptic Curve Cryptographic accelerator over GF(p). In: Irish Signals and Systems Conference (ISSC), pp. 589–594 (2004)Google Scholar
  31. 31.
    McLoone M., McCanny J.: High performance single-chip FPGA Rijndael algorithm implementations. In: Koç, Ç.K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162, pp. 65–76. Springer, Berlin (2001)CrossRefGoogle Scholar
  32. 32.
    McLoone M., McCanny J.: Rijndael FPGA implementations utilising look-up tables. J. VLSI Signal Process. 34(3), 261–275 (2003)CrossRefMATHGoogle Scholar
  33. 33.
    National Institute of Standards and Technology (NIST): Recommended Elliptic Curves for Federal Government Use, July 1999Google Scholar
  34. 34.
    National Institute of Standards and Technology (NIST): FIPS PUB 197: Advanced Encryption Standard (2001)Google Scholar
  35. 35.
    National Institute of Standards and Technology (NIST): Digital Signature Standard (DSS) (FIPS 186-3), June 2009Google Scholar
  36. 36.
    Orlando G., Paar C.: A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m). In: Koç, Ç.K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2000). LNCS, vol. 1965, pp. 41–56. Springer, Berlin (2000)CrossRefGoogle Scholar
  37. 37.
    Orlando G., Paar C.: A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware. In: Koç, Ç.K., Naccache, D., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2001). LNCS, vol. 2162., pp. 356–371. Springer, Berlin (2001)Google Scholar
  38. 38.
    Rouvroy, G., Standaert, F.-X., Quisquater, J.-J., Legat, J.-D.: Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: International Conference on Information Technology: Coding and Computing, vol. 2, p. 583 (2004)Google Scholar
  39. 39.
    Satoh A., Takano K.: A scalable dual-field Elliptic Curve cryptographic processor. IEEE Trans. Comput. 52(4), 449–460 (2003)CrossRefGoogle Scholar
  40. 40.
    Solinas, J.A.: Generalized mersenne numbers. Technical report, National Security Agency (NSA), September 1999. Available at http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.46.2133&rep=rep1&type=pdf
  41. 41.
    Standaert F.-X., Rouvroy G., Quisquater J.-J., Legat J.-D.: Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003). LNCS, vol. 2779, pp. 334–350. Springer, Berlin (2003)CrossRefGoogle Scholar
  42. 42.
    Suzuki D.: How to Maximize the Potential of FPGA Resources for Modular Exponentiation. In: Paillier, P., Verbauwhede, I. (eds) Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES 2007), LNCS, vol. 4727, pp. 272–288. Springer, Berlin (2007)CrossRefGoogle Scholar
  43. 43.
    Xilinx Inc: UG190: Virtex-5 User Guide (2006). Available at http://www.xilinx.com/support/documentation/user_guides/ug190.pdf
  44. 44.
    Xilinx Inc: Xilinx’ History of FPGA Development (2008). Available at http://www.xilinx.com/company/history.htm
  45. 45.
    Xilinx Inc: Xilinx Spartan-3 and Virtex FPGA devices (2008). Available at http://www.xilinx.com/products/silicon_solutions/

Copyright information

© Springer-Verlag 2011

Authors and Affiliations

  1. 1.Horst Görtz Institute for IT SecurityRuhr-UniversitätBochumGermany

Personalised recommendations