3D analytical modeling and electrical characteristics analysis of gate-engineered SiO2/HfO2-stacked tri-gate TFET
- 24 Downloads
In this paper, we have incorporated the novel concept of gate material engineering in a three-dimensional tri-gate TFET structure with SiO2/HfO2-stacked gate oxide to reap the dual benefits of triple gate material and dielectric engineering in a single device. A detailed 3D analytical modeling of electrostatic potential distribution and electric field of the proposed structure is developed here solving 3D Poisson’s equation with suitable boundary conditions. Tunneling current is then extracted by integrating the band-to-band tunneling generation rate over the volume of the device. A comprehensive performance analysis of the present structure is analyzed in terms of potential profile, electric field and ON-current characteristics of the device by varying several parameters such as channel length, channel thickness, oxide thickness, applied gate and drain bias voltages. An overall performance comparison of the proposed structure with dual and single gate material equivalent tri-gate TFET structures with and without high-k gate stack is also demonstrated to explore the functional efficiency of the present structure. The results of the derived analytical model are compared with SILVACO ATLAS simulated data verifying the accuracy of our model in order to validate it for establishing the superiority of the structure.
KeywordsTFET 3D modeling Triple metal Kane’s model BTBT Gate stack
One of the authors, Priyanka Saha thankfully acknowledges this publication as an outcome of the R&D work undertaken project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation.
- A O Adan, T Naka, A Kagisawa, H Shimizu in SOI Conf. 1998, Proceedings, 1998 IEEE International (1998), p 9Google Scholar
- P Banerjee, A Mahajan, S K Sarkar, Devices for Integrated Circuit (DevIC), 2017 (2017), p 437Google Scholar
- A M Ionescu, K Boucart, K E Moselund, V Pott, D Tsamados, in Semiconductor Conference, 207, CAS 2007. International, vol 2 (2007) p 397Google Scholar
- K Goplakrishnan, P B Griffin, J DPlummer, in Electron Devices Meeting. IEDM’02. International (2002) p 289Google Scholar
- P Saha, S Sarkhel, S K Sarkar IEEE Tech. Rev. p 1 (2018)Google Scholar
- C Schulte-Braucks, S Richter, L Knoll, L Selmi, Q-T Zhao, S Mantl in Solid State Device Research Conference (ESSDERC), 2014 44th European (IEEE, 2014) p 178Google Scholar
- P Wu, J Zhang, L Zhang, Z Yu in Simulation of Semiconductor Processes and Devices (SISPAD), 2015 International Conference on (IEEE, 2015) p 317Google Scholar
- ATLAS: 2-D Device Simulator, SILVACO Int., Santa Clara, CA, USA 2013Google Scholar
- J Knoch, J Appenzeller in Device Research Conference Digest, 2005, DRC’05, 63rd, vol 1 (IEEE, 2005) p 153Google Scholar