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Indian Journal of Physics

, Volume 93, Issue 2, pp 197–205 | Cite as

Dual-material gate dual-stacked gate dielectrics gate-source overlap tri-gate germanium FinFET: analysis and application

  • Rajashree DasEmail author
  • Srimanta Baishya
Original Paper
  • 54 Downloads

Abstract

This study proposes a novel dual-material-gate dual-stacked-gate dielectrics gate–source overlap Ge FinFET and compares its characteristics with conventional FinFET. The proposed device shows very less leakage current (IOFF) (~ 10−17 A), significant on drain current (~ ION) (~ 10−4 A), very high ratio of ION to IOFF (ION/IOFF) (~ 1013) and less subthreshold swing of (SS) (71 mV/dec). This study presents the effect of different dielectrics, oxide thicknesses (tox) and back-gate voltages (VGB) on transfer characteristics of the proposed device. The effect of channel concentration on ION/IOFF, threshold voltage (Vth), transconductance (gm) and SS is also investigated. The effect of overlap length (Lov) on analog parameter, gate–source capacitance (Cgs), is also analyzed. Moreover, the effect of fin thickness (Tfin) on Vth and SS is also studied. The height of the BOX plays an important role in reducing IOFF. Moreover, with emphasis on digital application, by using the proposed device a digital inverter circuit is implemented, and this study investigates the characteristics using mixed-mode simulation.

Keywords

FinFET Dual-stacked-gate dielectrics Dual material gate Gate–source overlap 

PACS Nos.

85.30. − z 85.30.De 

References

  1. [1]
    G E Moore Electronics 38 33 (1965)Google Scholar
  2. [2]
    P M Zeitzoff and J E Chung IEEE Circuits Devices Mag. 21 4 (2005)CrossRefGoogle Scholar
  3. [3]
    T Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, B. Previtali, T. Ernst and S. Deleonibus, Solid-State Electron. 50 18 (2006)ADSCrossRefGoogle Scholar
  4. [4]
    T Ernst, C Tinella, C Raynaud and S Cristoloveanu Solid-State Electron. 46 373 (2002)ADSCrossRefGoogle Scholar
  5. [5]
    H S P Wong IBM J. Res. Dev. 46 133 (2002)CrossRefGoogle Scholar
  6. [6]
    T Y Chan, J Chen, P K Ko and C Hu Int. Electron Devices Meet. (Washington, DC, USA) p 718 (1987) Google Scholar
  7. [7]
    Y C Yeo, T-J King and C Hu IEEE Trans. Electron Devices 50 1027 (2003)ADSCrossRefGoogle Scholar
  8. [8]
    D Hisamoto, W-C Lee, J Kedzierski, H Takeuchi, K Asano, E Anderson, C Kuo, T-J King, J Bokor and C Hu IEEE Trans. Electron Devices 47 2320 (2000)ADSCrossRefGoogle Scholar
  9. [9]
    B Yu, L Chang, S Ahmed, H Wang, S Bell, C-Y Yang, C Tabery, C Ho, Q Xiang, T-J King, J Bokor, C Hu, M-R Lin and D Kyser Digest. Int. Electron Devices Meet. (San Francisco CA, USA) p 251 (2002)Google Scholar
  10. [10]
    J W Yang, P M Zeitzoff and H H Tseng IEEE Trans. Electron Devices 54 1464 (2007)ADSCrossRefGoogle Scholar
  11. [11]
    W K Yeh, W Zhang, Y-L Yang, A-N Dai, K Wu, T-H Chou, C-L Lin, K-J Gan, C-H Shih and P-Y Chen IEEE Trans. Device Mater. Reliab. 16 610 (2016)CrossRefGoogle Scholar
  12. [12]
    R Das, R Goswami and S Baishya Superlattices Microstruct. 91 51 (2016)ADSCrossRefGoogle Scholar
  13. [13]
    Y. Li, H.-M. Chou and J.-W. Lee IEEE Trans. Nanotechnol. 4 510 (2005)ADSCrossRefGoogle Scholar
  14. [14]
    M D Ko, C W Sohn, C K Baek and Y. H. Jeong IEEE Trans. Electron Devices 60 2721 (2013)ADSCrossRefGoogle Scholar
  15. [15]
    H Nam and C Shin IEEE Trans. Electron Devices 61 2007 (2014)ADSCrossRefGoogle Scholar
  16. [16]
    K M Tan, K-M Tan, T-Y Liow, R T P Lee, K M Hoe, C-H Tung, N Balasubramanian, G S Samudra and Y-C Yeo IEEE Electron. Device Lett. 28 905 (2007)ADSCrossRefGoogle Scholar
  17. [17]
    W Xu, H Yin, X Ma, P Hong, M Xu and L Meng Nanoscale Res. Lett. 10 249 (2015)ADSCrossRefGoogle Scholar
  18. [18]
    A R Degheidy, A M Elabsy, H G Abdelwahed and E B Elkenany Indian J. Phys. 86 363 (2012)ADSCrossRefGoogle Scholar
  19. [19]
    Sentaurus Device User, Synopsys p. 2009 (2009)Google Scholar
  20. [20]
    Y Tsividis and C M Andrew The four-terminal MOS transistor (New York: McGraw-Hill) p 208 (2011)Google Scholar
  21. [21]
  22. [22]
    R Saha, B Bhowmick and S Baishya IEEE Trans. Electron Devices 64 969 (2017)ADSCrossRefGoogle Scholar

Copyright information

© Indian Association for the Cultivation of Science 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNational Institute of Technology SilcharSilcharIndia

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