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Magnetic Field Effect on Threshold Voltage for Ultrathin Silicon Gate-All-Around Nanowire Field-Effect-Transistors

  • Hamdy AbdelhamidEmail author
  • Azza M. Anis
  • Mohamed E. Aboulwafa
  • Mohamed I. Eladawy
Original Paper
  • 23 Downloads

Abstract

Gate-all-around silicon nanowire field-effect-transistors (GAA Si NWFETs) received much interest in nanoscale electronic based systems and sensor applications. In this work, the threshold voltage for the ultrathin lightly doped n-channel Si GAA NWFETs with magnetic field effect is investigated. The study begins by modeling the inversion charge density including confinement-effect in the channel cross-section of the device. Three-dimensional (3D) potential model including magnetic field interaction is studied in this work. Threshold voltage and short channel effects such as threshold voltage roll-off and drain induced barrier lowering are also analyzed at different channel lengths. The obtained analytical results have been verified with 3D COMSOL numerical simulation results. The impact of the external magnetic field is well observed in the energy dispersion relations. However, the magnetic field has no considerable effect on the threshold voltage neither the short channel behavior for the proposed Si GAA NWFET even with increasing the biasing values and at different device parameters.

Keywords

Ultrathin Si GAA NWFETs Threshold voltage Short channel effects Zeeman effect Quantum confinement 

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References

  1. 1.
    Elhamid HA, Deen MJ (2008) Continuous current and surface potential models for undoped and lightly doped double-gate metal-oxide-semiconductor field-effect-transistors. J Appl Phys 103:114501–1–114501-13Google Scholar
  2. 2.
    Saremi M, Kusha AA, Mohammadi S (2012) Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits. Microelectron Eng 95:74–82CrossRefGoogle Scholar
  3. 3.
    Elthakeb AT, Elhamid HA, Ismail Y (2015) Scaling of TG-FinFETs: 3-D monte carlo simulations in the ballistic and quasi-ballistic regimes. IEEE Trans Electron Devices 62:1796–1802CrossRefGoogle Scholar
  4. 4.
    Imenabadi RM, Saremi M, Vandenberghe WG (2017) A novel pnpn-like z-shaped tunnel field-effect transistor with improved ambipolar behavior and RF performance. IEEE Trans Electron Devices 64:4752–4758CrossRefGoogle Scholar
  5. 5.
    Abadi RMI, Saremi M (2018) A resonant tunneling nanowire field effect transistor with physical contractions: a negative differential resistance device for low power very large scale integration applications. J Electron Mater 47:1091–1098CrossRefGoogle Scholar
  6. 6.
    Elhamid HA, Iniguez B, Guitart JR (2007) Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans Electron Devices 54:572–579CrossRefGoogle Scholar
  7. 7.
    Yeh MS, Lee YJ, Hung MF, Liu KC, Wu YC (2013) High-performance gate-all-around poly-Si thin-film transistors by microwave annealing with NH3 plasma passivation. IEEE Trans Nanotechnol 12:636–640CrossRefGoogle Scholar
  8. 8.
    Kumar S, Kumari A, Das MK (2016) Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications. J Comput Electron 16:47–60CrossRefGoogle Scholar
  9. 9.
    Nagy D, Indalecio G, Loureiro AJG, Elmessary MA, Kalna K, Seoane N (2018) FinFET versus gate-all-around nanowire FET: performance, scaling, and variability. IEEE J Electron Dev Soc 6:332–340CrossRefGoogle Scholar
  10. 10.
    Panda SR, Sharma R, Pradhan KP, Sahu PK (2016) Junctionless GAA nanowire transistor: towards circuit application. Int Conf ICEE, 1–4Google Scholar
  11. 11.
    Prakash O, Beniwal S, Maheshwaram S, Bulusu A, Singh N, Manhas SK (2017) Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits. IEEE Trans Device Mater Reliab 17:404–413CrossRefGoogle Scholar
  12. 12.
    Yao J, Li J, Luo K, Yu J, Zhang Q, Hou Z, Gu J, Yang W, Wu Z, Yin H, Wang W (2018) Physical insights on quantum confinement and carrier mobility in Si, Si0.45Ge0.55, Ge gate-all-around NSFET for 5 nm technology node. IEEE J Electron Dev Soc 6:841–848CrossRefGoogle Scholar
  13. 13.
    Bayani AH, Dideban D, Voves J, Moezi N (2017) Investigation of sub-10nm cylindrical surrounding gate germanium nanowire field effect transistor with different cross-section areas. Superlattices Microstruct 105:110–116CrossRefGoogle Scholar
  14. 14.
    Bayani AH, Voves J, Dideban D (2018) Effective mass approximation versus full atomistic model to calculate the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET). Superlattices Microstruct 113:769–776CrossRefGoogle Scholar
  15. 15.
    Gaidhane AD, Pahwa G, Verma A, Chauhan YS (2018) Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor. IEEE Trans Electron Devices 65:2024–2032CrossRefGoogle Scholar
  16. 16.
    Nayak K, Agarwal S, Bajaj M, Mural KVRM, Rao VR (2015) Random dopant fluctuation induced variability in undoped channel Si gate all around nanowire n-MOSFET. IEEE Trans Electron Devices 62:685–688CrossRefGoogle Scholar
  17. 17.
    Sung WL, Chao PJ, Li Y (2017) Timing and power fluctuations on gate-all-around nanowire CMOS circuit induced by various sources of random discrete dopants. Int Conf SISPADGoogle Scholar
  18. 18.
    Elkashlan RY, Elhamid HA, Ismail YI (2018) Two-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs. IET Circuits Dev Syst 12:341–346CrossRefGoogle Scholar
  19. 19.
    Michetti P, Mugnaini G, Iannaccone G (2009) Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime. IEEE Trans Electron Devices 56:1402–1410Google Scholar
  20. 20.
    Sharma D, Vishvakarma SK (2012) Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions. Microelectron J 43:358–363CrossRefGoogle Scholar
  21. 21.
    Kumar PR, Mahapatra S (2011) Quantum threshold voltage modeling of short channel quad gate silicon nanowire transistor. IEEE Trans Nanotech 10:121–128CrossRefGoogle Scholar
  22. 22.
    Pricilla A, Pandian MK, Balamurugan NB (2013) Potential and quantum threshold voltage modeling of gate-all-around nanowire MOSFETs. Active and Passive Electronic ComponentsGoogle Scholar
  23. 23.
    Pandian MK, Balamurugan NB (2014) Analytical threshold voltage modeling of surrounding gate silicon nanowire transistors with different geometries. J Electr Eng Technol 9:2079–2088CrossRefGoogle Scholar
  24. 24.
    Khan SUZ, Hossain MS, Hossen MO, Rahman FU, Zaman R, Khosru QDM (2014) Self-consistent capacitance-voltage characterization of gate-all-around graded nanowire transistor. arXiv:1406.5257v1 [cond-mat.mtrl-sci]
  25. 25.
    Jit S, Samoju VR, Tiwari PK (2014) A quasi-3D threshold voltage model for dual-metal quadruple-gate MOSFETs. Chin Phys Lett 31:128502–1-128502-3Google Scholar
  26. 26.
    Dubey S, Samoju VR, Tiwari PK (2015) Quasi-3D subthreshold current and subthreshold swing models of dual-metal quadruple-gate (DMQG) MOSFETs. J Comput Electron 14:582–592CrossRefGoogle Scholar
  27. 27.
    Samoju VR, Tiwari PK (2016) Threshold voltage modeling for dual-metal quadruple-gate (DMQG) MOSFETs. Int J Numer Model 29:695–706CrossRefGoogle Scholar
  28. 28.
    Mahapatra K, Samoju VR, Tiwari PK (2017) Analytical modeling of subthreshold characteristics by considering quantum confinement effects in ultrathin dual-metal quadruple gate (DMQG) MOSFETs. Superlattices Microstruct 111:704–713CrossRefGoogle Scholar
  29. 29.
    Mongillo M, Spathis P, Katsaros G, Gentile P, Franceschi SD (2012) Multifunctional devices and logic gates with undoped silicon nanowires. Nano Lett 12:3074–3079CrossRefGoogle Scholar
  30. 30.
    Marchi MD, Zhang J, Frache S, Sacchetto D, Gaillardon PE, Leblebici Y, Micheli GD (2014) Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs. IEEE Electron Device Lett 35:880–882CrossRefGoogle Scholar
  31. 31.
    Zhang S, Lou L, Gu Y (2017) Development of silicon nanowire–based NEMS absolute pressure sensor through surface micromachining. IEEE Electron Device Lett 38:653–656CrossRefGoogle Scholar
  32. 32.
    Pratap Y, Kumar M, Kabra S, Haldar S, Gupta RS, Gupta M (2017) Analytical modeling of gate-all-around junctionless transistor based biosensor for detection of neutral biomolecule species. J Comput Electron 17:1–9Google Scholar
  33. 33.
    Ivezic T (2016) Nature of electric and magnetic fields; how the fields transform. arXiv:1508.04802v2 [physics.gen-ph]
  34. 34.
    Gupta P (2011) Comprehensive mathematics xi. Laxmi Publications (P) LTDGoogle Scholar
  35. 35.
    Harrison P, Valavanis A (2016) Quantum wells wires and dots: theoretical and computational physics of semiconductor nanostructures. WileyGoogle Scholar
  36. 36.
    Kim R, Lundstrom M (2011) Notes on Fermi-Dirac integrals. arXiv:0811.0116v4 [cond-mat.mes-hall]
  37. 37.
    Elhamid HA, Iniguez B, Kilchytska V, Flandre D, Ismail Y (2015) An analytical 3D model for short-channel effects in undoped FinFETs. J Comput Electron 14:500–505CrossRefGoogle Scholar
  38. 38.
    Gradshteyn IS, Ryzhik IM (2014) Tables of integrals, series and products. Academic PressGoogle Scholar
  39. 39.
    Chiang TK (2009) A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs. Solid-State Electron 53:490–496CrossRefGoogle Scholar
  40. 40.
    Pradhan KP, Kumar MR, Mohapatra SK, Sahu PK (2015) Analytical modeling of threshold voltage for cylindrical gate all around (CGAA) MOSFET using center potential. Ain Shams Eng J 6:1171–1177CrossRefGoogle Scholar
  41. 41.
    Tiwari PK, Dubey S, Singh M, Jit S (2010) A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors. J Appl Phys 108:074508–1-074508-8CrossRefGoogle Scholar
  42. 42.
    COMSOL Multiphysics. http://www.comsol.com
  43. 43.
    Konakov AA, Ezhevskii AA, Soukhorukov AV, Guseinov DV, Popkov SA, Burdov VA (2011) Lande factor of the conduction electrons in silicon: temperature dependence. J Phys Conf Ser.  https://doi.org/10.1088/1742-6596/324/1/012027
  44. 44.
    Giorgioni A, Paleari S, Cecchi S, Vitiello E, Grilli E, Isella G, Jantsch W, Fanciulli M, Pezzoli F (2016) Strong confinement-induced engineering of the g-factor and lifetime of conduction electron spins in Ge quantum wells. Nat Commun.  https://doi.org/10.1038/ncomms13886
  45. 45.
    Kosaka H, Kiselev AA, Baron FA, Kim KW, Yablonovitch E (2001) Electron g factor engineering in IlI-V semiconductors for quantum communications. Electron Lett 37:464–465CrossRefGoogle Scholar
  46. 46.
    Litvinenko KL, Nikzad L, Pidgeon CR, Allam J, Cohen LF, Ashley T, Emeny M, Zawadzki W, Murdin BN (2008) Temperature dependence of the electron Lande g factor in InSb and GaAs. Phys Rev B 77:033204–1-033204-4CrossRefGoogle Scholar
  47. 47.
    Qu F, Veen J, Vries FK, Beukman AJA, Wimmer M, Yi W, Kiselev AA, Nguyen BM, Sokolich M, Manfra MJ, Nichele F, Marcus CM, Kouwenhoven LP (2016) Quantized conductance and large g-factor anisotropy in InSb quantum point contacts. Nano Lett 16:7509–7513CrossRefGoogle Scholar
  48. 48.
    Hofflin J, Sander C, Gieschke P, Greiner A, Korvink JG (2015) Subthreshold CMOS transistors are largely immune to magnetic field effects when operated above 11 T. Concepts Magn Reson Part B: Magn Reson Eng 45:97–105CrossRefGoogle Scholar
  49. 49.
    Shin M, Lee S, Klimeck G (2010) Computational study on the performance of Si nanowire PMOSFETs based on the k.p method. IEEE Trans Electron Devices 57:2274–2283CrossRefGoogle Scholar

Copyright information

© Springer Nature B.V. 2019

Authors and Affiliations

  1. 1.Center of Nano-Electronics and Devices (CND)Zewail City of Science and Technology6th October CityEgypt
  2. 2.Electrical Engineering Department, Faculty of EngineeringAjman UniversityAjmanUnited Arab Emirates
  3. 3.Electronics, Communications, and Computers Department, Faculty of EngineeringHelwan UniversityHelwanEgypt

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