For experiencing phenomenon at nanoscale regimes, Nanotube FETs have been explored quite attentively due to their ever-increasing application in low power electronics. Nanotubes have a unique property of forming a Gate All around configuration, which imparts the device with appropriate electrostatic control and at the same time providing it with a superior exemption from short channel effects. In this letter, we have proposed a Hetero Metal (HM)-Dual Gate (DG) All around Core-Shell (CS) Nanotube (NT) TFET. Different metal work functions for both the core and shell gates have been employed and compared the proposed device with a Single Metal Gate All around configuration. The HM-DG NT-TFET yielded better analog and RF characteristics like better ION (2.68X10−6A/μm), improved ION/IOFF (4.66X1012) and Subthreshold slope (19 mV/dec). The proposed device showed almost identical Cgg when compared to the Single Metal (SM) NT-TFET although transconductance (gm) and unity gain frequency (fT) were found to be far better than Single-Metal GAA Configuration that indicates towards the device being a propitious candidate in RF circuits. The devices were also compared based on linear parameters for which the proposed device exhibited superior results.
Hetero metal Dual-gate Nanotube Core-Shell Linear parameters
This is a preview of subscription content, log in to check access.
Bhuwalka K, Schulze J, Eisele I (2005) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering. IEEE Trans Electron Devices 52(5):909–917CrossRefGoogle Scholar
Baksh SS, Sarin RK, Amin SI, Anand S (2018) Design of GaAs based Junctionless field effect transistor and its performance evaluation. J Nanoelectron Optoelectron 13(1):32–37CrossRefGoogle Scholar
Jain N, Raj B (2018) Parasitic capacitance and resistance model development and optimization of raised source/drain SOI fin FET structure for analog circuit applications. J Nanoelectron Optoelectron 13(4):531–539CrossRefGoogle Scholar
Bhuwalka K, Schulze J, Eisele I (2005) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering. IEEE Trans Electron Devices 52(5):909–917CrossRefGoogle Scholar
Jain N, Raj B (2018) Parasitic capacitance and resistance model development and optimization of raised source/drain SOI FinFET structure for analog circuit applications. J Nanoelectron Optoelectron 13(4):531–539CrossRefGoogle Scholar
Jhaveri R, Nagavarapu V, Woo JCS (2011) Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans Electron Devices 58(1):80–86CrossRefGoogle Scholar
Kumar N, Raman A (2019) Design and investigation of charge-plasma-based work function engineered dual-metal-heterogeneous gate Si-Si0.55Ge0.45 GAA-cylindrical NWTFET for Ambipolar analysis. IEEE Trans Electron Devices 66(3):1468–1474CrossRefGoogle Scholar
Kumar SP, Agrawal A, Chaujar R et al (2011) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron Reliab 53:587–596CrossRefGoogle Scholar
Ghosh P, Haldar S, Gupta RS et al (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans Electron Devices 59:3263–3268CrossRefGoogle Scholar
Woerlee PH, Knitel MJ, Langevelde RV et al (2001) RF-CMOS performance trends. IEEE Trans Electron Devices 48:1776–1782CrossRefGoogle Scholar
Niu G, Liang Q, Cressler JD et al (2001) RF linearity characteristics of SiGe HBTs. IEEE Trans Microw Theory Tech 49:1558–1565CrossRefGoogle Scholar
Kang S, Choi B, Kim B (2003) Linearity analysis of CMOS for RF application. IEEE Trans Microw Theory Tech 51:972–977CrossRefGoogle Scholar