Advertisement

Silicon

pp 1–11 | Cite as

An Optimized Ge Pocket SOI JLT with Efforts to Improve the Self-Heating Effect: Doping & Materials Perspective

  • Vishnu Priya Ammina
  • Shiva Prasad Vankudothu
  • Rameez Raja Shaik
  • K. P. PradhanEmail author
Original Paper
  • 13 Downloads

Abstract

An approach is demonstrated to improve the performance of conventional SOI JLT (Silicon-on-Insulator Junctionless Transistor) i.e., to increase the on-off ratio with an effort to improve the self-heating effect. A small germanium pocket is introduced in the channel region resulting in three different regions namely source, pocket and channel-drain. The behavior of SOI JLT with different source materials is performed to determine the most favorable one. The doping concentrations of all three regions are also optimized to achieve superior performance. Later all the designs are compared with the reference SOI JLT to choose the optimum one. The device with SiGe as source and Ge in the pocket region is considered as the potential model as it is predicting excellent on-off ratio (order of 106). The size and position of the pocket is evaluated by observing the device characteristics. Further, the importance of SHE (Self Heating Effect) in SOI JLT is demonstrated. To reduce the lattice temperature, one imperative solution is proposed in the SOI platform. Various analysis like analog/RF, temperature analysis including the evaluation of ZTC (Zero Temperature Coefficient) are performed for the optimized device architecture.

Keywords

SOI JLT Leakage current Pocket Doping concentration SHE Undoped silicon 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Notes

Acknowledgments

Thanks to Dr. S R Routray, SRM Institute of Science and Technology, for providing the simulation tool. Special mention to Mr. Chandrasekar L in extending their helping hand to carry forward the work.

References

  1. 1.
    Gundapaneni S, Kottantharayil PA, Ganguly PS (2012) Investigation of junction-less transistor (jlt) for cmos scaling. Indian Institute of Technology-BombayGoogle Scholar
  2. 2.
    Zhang K (2009) Embedded memories for nano-scale VLSIs, vol 2. SpringerGoogle Scholar
  3. 3.
    Schaller RR (1997) Moore’s law: past, present and future. IEEE Spectrum 34(6):52–59CrossRefGoogle Scholar
  4. 4.
    Mack CA (2011) Fifty years of moore’s law. IEEE Trans Semicond Manuf 24(2):202–207CrossRefGoogle Scholar
  5. 5.
    Shahidi GG (2007) Evolution of cmos technology at 32 nm and beyond. In: 2007 IEEE Custom integrated circuits conference. IEEE, pp 413–416Google Scholar
  6. 6.
    Adler E, DeBrosse JK, Geissler SF, Holmes SJ, Jaffe MD, Johnson JB, Koburger CW, Lasky JB, Lloyd B, Miles GL et al (1995) The evolution of ibm cmos dram technology. IBM J Res Develop 39 (1.2):167–188CrossRefGoogle Scholar
  7. 7.
    Ryan JG, Geffken RM, Poulin NR, Paraszczak JR (1995) The evolution of interconnection technology at ibm. IBM J Res Dev 39(4):371–381CrossRefGoogle Scholar
  8. 8.
    Taur Y (2002) Cmos design near the limit of scaling. IBM J Res Dev 46(2.3):213–222CrossRefGoogle Scholar
  9. 9.
    Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Philip Wong H-S (2001) Device scaling limits of si mosfets and their application dependencies. Proc IEEE 89(3):259–288CrossRefGoogle Scholar
  10. 10.
    Baccarani G, Wordeman MR, Dennard RH (1984) Generalized scaling theory and its application to a 1/4 micrometer mosfet design. IEEE Trans Electron Dev 31(4):452–462CrossRefGoogle Scholar
  11. 11.
    Colinge J-P (2012) Junctionless transistors. In: 2012 IEEE International meeting for future of electron devices. IEEE, Kansai, pp 1–2Google Scholar
  12. 12.
    Solankia T, Parmar N (2011) A review paper: a comprehensive study of junctionless transistor. In: National conference on recent trends in engineering & technology, pp 13–14Google Scholar
  13. 13.
    Colinge J-P, Lee C-W, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’neill B, Blake A, White M et al (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225CrossRefGoogle Scholar
  14. 14.
    Colinge JP, Lee CW, Dehdashti Akhavan N, Yan R, Ferain I, Razavi P, Kranti A, Yu R (2011) Junctionless transistors: physics and properties. In: Semiconductor-on-insulator materials for nanoelectronics applications. Springer, pp 187–200Google Scholar
  15. 15.
    Lee CW, Ferain I, Kranti A, Dehdashti Akhavan N, Razavi P, Yan R, Yu R, O’Neill B, Blake A, White M et al (2010) Short-channel junctionless nanowire transistors. In: Proc. SSDM, pp 1044– 1045Google Scholar
  16. 16.
    Leung G, Chui CO (2012) Variability impact of random dopant fluctuation on nanoscale junctionless finfets. IEEE Electron Dev Lett 33(6):767–769CrossRefGoogle Scholar
  17. 17.
    Duarte JP, Choi S-J, Choi Y-K (2011) A full-range drain current model for double-gate junctionless transistors. IEEE Trans Electron Dev 58(12):4219–4225CrossRefGoogle Scholar
  18. 18.
    Rios R, Cappellani A, Armstrong M, Budrevich A, Gomez H, Pai R, Rahhal-Orabi N, Kuhn K (2011) Comparison of junctionless and conventional trigate transistors with l_{g} down to 26 nm. IEEE Electron Dev Lett 32(9):1170–1172CrossRefGoogle Scholar
  19. 19.
    Lahgere A, Kumar MJ (2017) A tunnel dielectric-based junctionless transistor with reduced parasitic bjt action. IEEE Trans Electron Dev 64(8):3470–3475CrossRefGoogle Scholar
  20. 20.
    Sahu SA, Goswami R, Mohapatra SK (2019) Characteristic enhancement of hetero dielectric dg tfet using sige pocket at source/channel interface: proposal and investigation. Silicon, 1–8Google Scholar
  21. 21.
    Bentrcia T, Djeffal F, Ferhati H, Dibi Z (2019) A comparative study on scaling capabilities of si and sige nanoscale double gate tunneling fets. Silicon, 1–9Google Scholar
  22. 22.
    Villalon A, Le Royer C, Nguyen P, Barraud S, Glowacki F, Revelant A, Selmi L, Cristoloveanu S, Tosti L, Vizioz C et al (2014) First demonstration of strained sige nanowires tfets with ion beyond 700μ a/μ m, 1–2Google Scholar
  23. 23.
    Li W, Woo JCS (2018) Optimization and scaling of ge-pocket tfet. IEEE Trans Electron Dev 65(12):5289–5294CrossRefGoogle Scholar
  24. 24.
    Strelcov E, Dmitriev S, Button B, Cothren J, Sysoev V, Kolmakov A (2008) Evidence of the self-heating effect on surface reactivity and gas sensing of metal oxide nanowire chemiresistors. Nanotechnology 19 (35):355502CrossRefGoogle Scholar
  25. 25.
    Semenov O, Vassighi A, Sachdev M (2006) Impact of self-heating effect on long-term reliability and performance degradation in cmos circuits. IEEE Trans Dev Mater Reliab 6(1):17–27CrossRefGoogle Scholar
  26. 26.
    Jenkins KA, Rim K (2002) Measurement of the effect of self-heating in strained-silicon mosfets. IEEE Electron Dev Lett 23(6):360–362CrossRefGoogle Scholar
  27. 27.
    Su LT, Chung JE, Antoniadis DA, Goodson KE, Flik MI (1994) Measurement and modeling of self-heating in soi nmosfet’s. IEEE Trans Electron Dev 41(1):69–75CrossRefGoogle Scholar
  28. 28.
    Ghaffari M, Orouji AA (2018) A novel nanoscale soi mosfet by embedding undoped region for improving self-heating effect. Superlatt Microstruct 118:61–78CrossRefGoogle Scholar
  29. 29.
    Device Simulator Atlas (2005) Atlas user’s manual. Silvaco International Software, Santa Clara, CA, USAGoogle Scholar

Copyright information

© Springer Nature B.V. 2019

Authors and Affiliations

  1. 1.Indian Institute of Information Technology Design and Manufacturing (IIITDM) KancheepuramChennaiIndia

Personalised recommendations