Influence of Source Stack and Heterogeneous Gate Dielectric on Band to Band Tunneling Rate of Tunnel FET
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In this paper, the presence of source stack and heterogeneous gate dielectric material in the structure of an n-channel tunnel FET (TFET) is investigated. P+ type source stack above the source region causes an increase in the electric field which in turn leads to more band bending in the energy band diagram of the proposed structure. Therefore, the effective width of tunneling region decreases and as a result electron Band to Band Tunneling (BTBT) rate enhances. It is also shown that incorporating hetero gate dielectric material can further enhance BTBT rate in the source-channel region and it becomes more intensive as the permittivity of high-k dielectric is increased. The hetero gate structure which is utilized is a combination of SiO2 and a high-k material. Our simulation results indicate that the presence of SiO2 in the drain side minimizes ambipolar current at negative gate voltages. Simulations are performed using Silvaco Atlas TCAD for a channel length of 50 nm using nonlocal tunneling model.
KeywordsTFET Band to band tunneling Source stack Heterogeneous High-k Ambipolar conduction
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- 2.Taur Y, Ning TH (2009) Fundamentals of modern VLSI devices, 2nd edn. Cambridge University Press, New YorkGoogle Scholar
- 3.Weste NH, Harris D (2011) CMOS VLSI design: a circuits and systems perspective, 4th edn. Pearson Education, BostonGoogle Scholar
- 8.Mehrad M, Ghadi ES (2017) C-shape silicon window nanoMOSFET for reducing the short channel effects. In 2017 joint international EUROSOI workshop and international conference on ultimate integration on silicon (EUROSOI-ULIS), Athens, pp 164–167. https://doi.org/10.1109/ULIS.2017.7962572
- 9.Choi WY, Song JY, Lee JD, Park YJ, Park B-G (2005) 70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs). In 2007 IEEE international electron devices meeting (IEDM), Washington, pp 955–958. https://doi.org/10.1109/IEDM.2005.1609519
- 11.Kyung C-M (2016) Nano devices and circuit techniques for low-energy applications and energy harvesting. Springer Science & Business Media, DordrechtGoogle Scholar
- 13.S. I.Association (2015) International technology roadmap for semiconductors, https://www.semiconductors.org/resources/2015-international-technology-roadmap-for-semiconductors-itrs. Accessed 12 Sept 2019.
- 18.Krishnamohan T, Kim D, Raghunathan S, Saraswat K (2008) Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec subthreshold slope. In 2008 IEEE international electron devices meeting (IEDM), San Francisco, pp 1–3. https://doi.org/10.1109/IEDM.2008.4796839
- 19.Kim SH, Kam H, Hu C, Liu T-J K (2009) Germanium-source tunnel field effect transistors with record high ION/IOFF. In 2009 symposium on VLSI technology, Honolulu, pp 178–179, 15–17 June 2009 Google Scholar
- 20.D. S. Yadav, D. Sharma, B. R. Raad, and V. Bajaj, “Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis,” in Advanced Communication Control and Computing Technologies (ICACCCT), 2016 International Conference on, 2016, pp. 26–29Google Scholar
- 32.Colinge J-P (2004) Silicon-on-insulator technology: materials to VLSI, 3rd edn. Springer Science & Business Media, New YorkGoogle Scholar
- 33.Atlas DS (2016) Atlas user’s manual. Silvaco international software, Santa Clara, https://www.silvaco.com. Accessed 12 Sept 2019