3-D Analytical Modeling of Triple Metal Tri-Gate Graded Channel High-k SON TFET for Improved Performance
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In this paper, three dimensional analytical paradigm for triple metal graded channel high-k silicon-on-nothing tunnel field effect transistor (TM-TG GC-High-k SON TFET) is deduced in terms of surface potential, electric field and drain current parameters. 3-D Poisson’s equation and Kane’s model are solved considering popular parabolic surface potential approximation technique along with assuming suitable boundary conditions for deriving the aforementioned electrical characteristics of the device under consideration for evaluation of its short-channel performance. It is demonstrated that the proposed structure offers sharp band bending phenomenon at source-channel interface with application of appropriate gate bias to revamp the drive current. At the same time, it results larger tunneling width at the channel-drain interface to subdue the possibility of reverse tunneling as compared to other reported structures. The results predicted by the model are compared with simulation data to verify the exactness of the developed analytical model. Further, the device is optimized in respect of selecting metal work function values and corresponding gate lengths along with adopting proper gate-stack combination (choice of high-k with SiO2) for enhanced performance.
KeywordsTriple metal graded channel (TM-GC) 3-D Poisson’s equation Tunneling width Gate-stack Silicon-on-nothing (SON) TFET Three-dimensional (3-D) modeling
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Priyanka Saha thankfully acknowledges the financial support as PhD fellow under “Visvesvaraya PhD Scheme”, DeitY, Government of India.
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