Advertisement

Silicon

pp 1–12 | Cite as

3-D Analytical Modeling of Triple Metal Tri-Gate Graded Channel High-k SON TFET for Improved Performance

  • Dinesh Kumar DashEmail author
  • Priyanka Saha
  • Subir Kumar Sarkar
Original Paper
  • 1 Downloads

Abstract

In this paper, three dimensional analytical paradigm for triple metal graded channel high-k silicon-on-nothing tunnel field effect transistor (TM-TG GC-High-k SON TFET) is deduced in terms of surface potential, electric field and drain current parameters. 3-D Poisson’s equation and Kane’s model are solved considering popular parabolic surface potential approximation technique along with assuming suitable boundary conditions for deriving the aforementioned electrical characteristics of the device under consideration for evaluation of its short-channel performance. It is demonstrated that the proposed structure offers sharp band bending phenomenon at source-channel interface with application of appropriate gate bias to revamp the drive current. At the same time, it results larger tunneling width at the channel-drain interface to subdue the possibility of reverse tunneling as compared to other reported structures. The results predicted by the model are compared with simulation data to verify the exactness of the developed analytical model. Further, the device is optimized in respect of selecting metal work function values and corresponding gate lengths along with adopting proper gate-stack combination (choice of high-k with SiO2) for enhanced performance.

Keywords

Triple metal graded channel (TM-GC) 3-D Poisson’s equation Tunneling width Gate-stack Silicon-on-nothing (SON) TFET Three-dimensional (3-D) modeling 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Notes

Acknowledgments

Priyanka Saha thankfully acknowledges the financial support as PhD fellow under “Visvesvaraya PhD Scheme”, DeitY, Government of India.

References

  1. 1.
    Khanna VK (2016) Integrated Nanoelectronics: Nanoscale CMOS, Post-CMOS and Allied Nanotechnologies, Springer India, Hardcover ISBN:978-81-322-3623-8, eBook ISBN: 978-81-322-3625-2, 451Google Scholar
  2. 2.
    Vandamme EP, Jansen P, Deferm L (1997) Modeling the Subthreshold Swing in MOSFET’s. IEEE Electron Dev Lett 18(8):369–371CrossRefGoogle Scholar
  3. 3.
    Moore GE (1965) Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 114Google Scholar
  4. 4.
    Pop E, Sinha S, Goodson KE (2006) Heat Generation and Transport in Nanometer-Scale Transistors, in Proceedings of the IEEE, Volume: 94, Issue: 8, Pages: 1587 - 1601CrossRefGoogle Scholar
  5. 5.
    Bangsaruntip S, Cohen GM, Majumdar A, Sleight JW (2010) Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Electron Dev Lett 31(9):903–905CrossRefGoogle Scholar
  6. 6.
    Müller RS, Kaminsand TI, Chan M (2003) Device Electronics for Integrated Circuits. Wiley, New York, NY, USA, pp 443–445Google Scholar
  7. 7.
    Zhang Q, Zhao W, Seabaugh A (2006) Low-subthreshold-swing tunnel transistors. IEEE Electron Dev Lett 27(4):297–300.  https://doi.org/10.1109/LED.2006.871855 CrossRefGoogle Scholar
  8. 8.
    Saurabh S, Kumar MJ (2010) Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability. IEEE Trans Device Mater Reliab 10(3):390–395.  https://doi.org/10.1109/TDMR.2010.2054095 CrossRefGoogle Scholar
  9. 9.
    Kumar MJ, Janardhanan S (2013) Doping-Less Tunnel Field Effect Transistor: Design and Investigation. IEEE Trans Electron Devices 60(10):3285–3290.  https://doi.org/10.1109/TED.2013.2276888 CrossRefGoogle Scholar
  10. 10.
    Boucart K, Ionescu AM (2007) Double-Gate Tunnel FET With High-$\kappa$Gate Dielectric. IEEE Trans Electron Devices 54(7):1725–1733.  https://doi.org/10.1109/TED.2007.899389 CrossRefGoogle Scholar
  11. 11.
    Toh E-H, Wang GH, Samudra G, Yeo Y-C (2008) Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications. J Appl Phys 103(10):104504.  https://doi.org/10.1063/1.2924413 CrossRefGoogle Scholar
  12. 12.
    Choi WY, Lee W (2010) Hetero-gate-dielectric tunneling field effect transistors. IEEE Trans Electron Devices 57(9):2317–2319.  https://doi.org/10.1109/TED.2010.2052167 CrossRefGoogle Scholar
  13. 13.
    Saha P, Sarkhel S and Sarkar SK (2018) Compact 3D Modeling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor, DOI:  https://doi.org/10.1080/02564602.2018.1428503, IETE Technical ReviewCrossRefGoogle Scholar
  14. 14.
    Bagga N, Sarkar SK (2015) An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET. IEEE Trans Electron Devices 62(7):2136–2142CrossRefGoogle Scholar
  15. 15.
    Dash DK, Saha P, Banerjee P and Sarkar SK (2018) Analytical Modeling of Graded Metal Graded Dielectric Silicon-On-Nothing TFET -A Comparative Study” in IEEE International Conference on Computing, Power and Communication Technologies (GUCON) 2018, 28th-29th September, Greater Noida, Uttar Pradesh, India (accepted)Google Scholar
  16. 16.
    Upasana RN, Saxena M, Gupta M (2015) Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications. in IEEE Trans Electron Devices 62(10):3348–3356.  https://doi.org/10.1109/TED.2015.2462743 CrossRefGoogle Scholar
  17. 17.
    Dash DK, Saha P and Sarkar SK (2017) Analytical Modeling of Asymmetric hetero-dielectric engineered dual-material DG-TFET, J Comput Electron, Springer, DOI 10.1007/s 10825-017-1102-8, 08 NovemberGoogle Scholar
  18. 18.
    Saha P, Banerjee P and Sarkar SK (2018) "2D modeling based comprehensive analysis of short channel effects in DMG strained VSTB FET", Superlattices and Microstructures, Elsevier, doi. https://doi.org/10.1016/j.spmi.2018.03.070, vol. 118, pp-16-28CrossRefGoogle Scholar
  19. 19.
    Kumari T, Saha P, Dash DK, Sarkar SK (2018) Modeling of Dual Gate Material Hetero-dielectric Strained PNPN TFET for Improved ON Current. J Mater Eng Perform 27(6):2747–2753CrossRefGoogle Scholar
  20. 20.
    Banerjee P and Sarkar SK (2017) "3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects", in Journal of Computational Electronics, Springer, Vol.16.No.3,pp-631-639
  21. 21.
    Saha P, Sarkhel S, Dash DK, Senapati S and Sarkar SK, Analytical Modeling and Simulation of Triple Metal Front Gate Stack DG- MOSFET with Graded channel (GC-TMDG MOSFET), International Conference on Communication Devices and Networking (ICCDN) 2017, Sikkim Manipal Institute of Technology, Majhitar, Sikkim, 3-4th June, 2017(Best Paper Awarded). Published as book chapter in Advances in Communication, Devices and Networking in Lecture Notes in Electrical Engineering, pp-97-105, Vol.462, ISBN 978-981-10-7901-6Google Scholar
  22. 22.
    Dash DK, Saha P, Mahajan A and Sarkar SK (2017) 3-D analytical modeling of dual-metal front-gate stack tri-gate SON-TFET with graded channel engineering, IEEE Calcutta Conference (CALCON), Kolkata, 2017, pp. 199-204.doi:  https://doi.org/10.1109/CALCON.2017.8280724
  23. 23.
    Chander S, Baishya S (2015) A Two-Dimensional Gate Threshold Voltage Model for a Heterojunction SOI-Tunnel FET With Oxide/Source Overlap. IEEE Electron Device Lett 36(7):714–716.  https://doi.org/10.1109/LED.2015.2432061 CrossRefGoogle Scholar
  24. 24.
    Beneventi GB, Gnani E, Gnudi A, Reggiani S, Baccarani G (2014) Dual-metal-gate InAs Tunnel FET with enhanced turn-on steepness and high ON-current. IEEE Trans Electron Devices 61:776–784.  https://doi.org/10.1109/TED.2014.2298212 CrossRefGoogle Scholar
  25. 25.
    Kumar S et al (2017) 2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices 64(3):960–968.  https://doi.org/10.1109/TED.2017.2656630 CrossRefGoogle Scholar
  26. 26.
    Banerjee P, Saha P and Sarkar SK (2018) Analytical Modeling and Performance Analysis of Gate Engineered Tri-gate SON MOSFET, IET Circuits, Devices & Systems, DOI:  https://doi.org/10.1049/iet-cds.2017.0473 CrossRefGoogle Scholar
  27. 27.
    Schulte-Braucks C, Richter S, Knoll L, Selmi L, Zhao Q-T, Mantl S (2015) Experimental demonstration of improved analog device performance of nanowire-TFETs. Solid State Electron 113:179–183CrossRefGoogle Scholar
  28. 28.
    Jurczak M, Skotnicki T, Gwoziecki R, Paoli M, Tormen B, Ribot P et al (2001) Dielectric pockets—a new concept of the junctions for deca-nanometric CMOS devices. IEEE Trans Electron Dev 48:1770–1774CrossRefGoogle Scholar
  29. 29.
    Sato T, Aoki N, Mizushima I, Tsunashima Y (1999) A new substrate engineering for the formation of empty space in silicon (ESS) induced by silicon surface migration. IEDM Tech Dig 517–20Google Scholar
  30. 30.
    Monfray S, Skotnicki T, Morand Y (2001) First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance. IEDM Tech Dig 645–8Google Scholar
  31. 31.
    Bu W-H, Huang R, Li M (2006) Silicon–on-nothing MOSFETs fabricated with hydrogen and helium co-implantation. Chin Phys 15(11):2751–2755CrossRefGoogle Scholar
  32. 32.
    Pavanello MA, Martino JA, Dessard V, Flandre D (2000) Graded-channel fully depleted silicon-on-insulators nMOSFET for reducing the parasitic bipolar effects. Solid State Electron 44(6):917–922CrossRefGoogle Scholar
  33. 33.
    Kranti A, Ming Chung T, Flandre D, Raskin J-P (2004) Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications. Solid State Electron 48:947–959CrossRefGoogle Scholar
  34. 34.
    Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs. IEEE Trans Electron Devices 63(3):966–973.  https://doi.org/10.1109/TED.2016.2520096 CrossRefGoogle Scholar
  35. 35.
    Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Dev 36(2):399–402CrossRefGoogle Scholar
  36. 36.
    Vishnoi R, Kumar MJ (2014) Compact Analytical Drain Current Model of Gate-All-Around Nanowire Tunneling FET. IEEE Trans Electron Devices 61(7):2599–2603.  https://doi.org/10.1109/TED.2014.2322762 CrossRefGoogle Scholar
  37. 37.
    Wang H et al (2014) A novel barrier controlled Tunnel FET. IEEE Electron Device Lett 35(7):798–800CrossRefGoogle Scholar

Copyright information

© Springer Nature B.V. 2019

Authors and Affiliations

  • Dinesh Kumar Dash
    • 1
    Email author
  • Priyanka Saha
    • 1
  • Subir Kumar Sarkar
    • 1
  1. 1.Department of Electronics and Telecommunication EngineeringJadavpur UniversityKolkataIndia

Personalised recommendations