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Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET)

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Abstract

In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the effect of substrate-induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. Such changes render difference in potential between substrate bulk and surface. The channel potential has been modelled using the parabolic approximation method. The developed model is useful for the optimization of short-channel effects for SOI JLFETs. The substrate bias voltage as a fourth terminal is found to be a powerful tool for tuning the threshold voltage for different device parameters variation. The model results are in good agreement with the simulation results obtained from Sentaurus TCAD simulator.

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Correspondence to Sarvesh Dubey.

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Dixit, V.K., Gupta, R., Purwar, V. et al. Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET). Silicon (2019). https://doi.org/10.1007/s12633-019-00185-7

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Keywords

  • JLFET
  • Threshold voltage
  • SOI
  • Substrate bias
  • FET