In the present paper, a threshold voltage model of short channel silicon-on-insulator (SOI) Junctionless Field Effect Transistors (JLFETs) has been presented. The model includes the effect of substrate-induced surface potential (SISP) effect on threshold voltage with necessary changes in the boundary conditions at the silicon-buried oxide (BOX) interface. Such changes render difference in potential between substrate bulk and surface. The channel potential has been modelled using the parabolic approximation method. The developed model is useful for the optimization of short-channel effects for SOI JLFETs. The substrate bias voltage as a fourth terminal is found to be a powerful tool for tuning the threshold voltage for different device parameters variation. The model results are in good agreement with the simulation results obtained from Sentaurus TCAD simulator.
This is a preview of subscription content, log in to check access.
Buy single article
Instant access to the full article PDF.
Price includes VAT for USA
Subscribe to journal
Immediate online access to all issues from 2019. Subscription will auto renew annually.
This is the net price. Taxes to be calculated in checkout.
Colinge J-P, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229
Taur Y, Chen H-P, Wang W, Lo S-H, Wann C (2012) On–off charge–voltage characteristics and DopantNumber fluctuation effects in Junctionless double-gate MOSFETs. IEEE Trans Electron Devices 59:863–866
Sahay S, Kumar MJ (2016) Realizing efficient volume depletion in SOI Junctionless FETs, J. Elect Dev Society 4:110–115
Celler GK (2003) Frontiers of silicon-on-insulator. J Appl Physiol 93:4955–4978
Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S (2016) Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. IEEE Trans Electron Devices 63:2299–2305
Chiang T-K (2012) A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans Electron Devices 59:2284–2289
Jiang C, Liang R, Wang J, Xu J (2015) A two-dimensional analytical model for short channel junctionless double-gate MOSFETs. AIP Adv 5:57122–1–57122-13
Imam MA, Osman MA, Osman AA (1999) Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects. Microelectron Reliab 39:487–495
Gola D, Singh B, Tiwari PK (2017) A threshold voltage model of tri-GateJunctionless field-effect TransistorsIncluding substrate Bias effects. IEEE Trans Elec Dev 64:3534–3540
Kumar A, Tiwari PK (2014) A threshold voltage model of short channel fully-depleted recessed-source/drain (re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects. Solid State Electron 95:52–60
Woo J-H, Choi J-M, Choi Y-K (2013) Analytical threshold voltage model of junctionless double-gate MOSFETs with localized charges. IEEE Trans Elec Dev 60:2951–2955
Sim J-H, Kuo JB (1993) An analytical back-gate bias effect model for ultrathin SOI CMOS devices. IEEE Trans Elec Dev 40:755–765
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
About this article
Cite this article
Dixit, V.K., Gupta, R., Purwar, V. et al. Effect of Substrate Induced Surface Potential (SISP) on Threshold Voltage of SOI Junction-Less Field Effect Transistor (JLFET). Silicon (2019). https://doi.org/10.1007/s12633-019-00185-7
- Threshold voltage
- Substrate bias