Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in Strained SOI-FinFET

  • 29 Accesses

  • 1 Citations


In the recent sub-20 nm technology node, the process variability issues have become a major problem for scaling of MOS devices. We present a design for a strained Si/SiGe FinFET on an insulator using a 3D TCAD simulator. The impact of metal gate work function variability (WFV) on electrical parameters is studied. Such impact of WFV for different mole fractions (x) of the SiGe layer in a strained SOI-FinFET with varying grain size is presented. The results show that as the mole fraction is increased, the variability in threshold voltage (σVT) and off current (σIoff) is decreased; while, the variability of on-current (σIon) is increased. A notable observation is the distribution of electrical parameters approaches a normal distribution for smaller grain sizes.

This is a preview of subscription content, log in to check access.


  1. 1.

    Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–287.

  2. 2.

    Bhattacharya D, Jha NK, (2014) “FinFETs: from devices to architectures,” Hindawi Publishing Corporation, Advances in Electronics Article ID 365689, 21 pages,

  3. 3.

    Narendar V, Rai S, Tiwari S (2016) A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET. J Comput Electron 15:1316–1325

  4. 4.

    Li C, Zhuang Y, Zhang L (2012) Simulation study on FinFET with tri-material gate, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), Bangkok, pp. 1–3.

  5. 5.

    Yeh M-S, Wu Y-C, Hung M-F, Liu K-C, Jhan Y-R, Chen L-C, Chang C-Y (2013) Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory. Nanoscale Res Lett 8(1):331

  6. 6.

    Mehrad M, Orouji AA (2010) Partially cylindrical fin field-effect transistor: a novel device for nanoscale applications. IEEE Trans Device Mater Reliab 10(2):271–275

  7. 7.

    T. Irisawa, K. Okano, T. Horiuchi, H. Itokawa, I. Mizushima, K. Usuda, T. Tezuka, N. Sugiyama, S.I. Takagi, (Aug. 2009) Electron mobility and short-channel device characteristics of SOI FinFETs with Uniaxially strained (110) channels, in IEEE Trans Electron vol. 56, no. 8, pp. 1651–1658,

  8. 8.

    Liao YB, Chiang MH, Lai YS, Hsu WC (2014) Stack gate technique for doping less bulk FinFETs. IEEE Trans Electron Devices 61(4):963–968

  9. 9.

    Mizuno T, Takagi S, Sugiyama N, Satake H, Kurobe A, Toriumi A (May 2000) Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology. IEEE Electron Device Lett 21(5):230–232.

  10. 10.

    Uchida K, Krishnamohan T, Saraswat KC, Nishi Y (2005) Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, Washington, DC, pp 129–132.

  11. 11.

    Dubey S, Kondekar PN (2017) Asymmetrically doped stacked channel strained SOI FinFET. Superlattice Microst 102:74–78

  12. 12.

    Lizzit D, Palestri P, Esseni D, Revelant A, Selmi L (June 2013) Analysis of the performance of n-type FinFETs with strained SiGe Channel. IEEE Trans. Electron Devices 60(6):1884–1891.

  13. 13.

    Chiang M, Lin J, Kim K, Chuang C (Aug. 2007) Random dopant fluctuation in limited-width FinFET technologies. IEEE Trans. Electron Devices 54(8):2055–2060.

  14. 14.

    Leung G, Chui CO (Oct. 2013) Interactions between line edge roughness and random dopant fluctuation in nonplanar field-effect transistor variability. IEEE Trans. Electron Devices 60(10):3277–3284.

  15. 15.

    Brown AR, Idris NM, Watling JR, Asenov A (2010) Impact of metal gate granularity on threshold voltage variability: a full-scale three-dimensional statistical simulation study. IEEE Electron Device Lett 31(11):1199–1201

  16. 16.

    Ohmori K et al (2008) Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates. 2008 IEEE international Electron devices meeting, San Francisco, pp 1–4.

  17. 17.

    Nawaz SM, Dutta S, Chattopadhyay A, Mallik A (June 2014) Comparison of random dopant and gate-metal Workfunction variability between junctionless and conventional FinFETs. IEEE Electron Device Lett 35(6):663–665

  18. 18.

    Nawaz SM, Mallik A (Aug. 2016) Effects of Device scaling on the performance of junctionless FinFETs due to gate-metal work function variability and random dopant fluctuations. IEEE Electron Device Lett 37(8):958–961

  19. 19.

    Saha R, Bhowmick B, Baishya S (March 2017) Statistical dependence of gate metal work function on various electrical parameters for an n-channel Si step-FinFET. IEEE Trans Electron Devices 64(3):969–976.

  20. 20.

    Dadgour HF, Endo K, De VK, Banerjee K (2010) Grain-orientation induced work function variation in nanoscale metal-gate transistors-part I: modeling, analysis, and experimental validation. IEEE Trans Electron Devices 57(10):2504–2514

  21. 21.

    Rathore RS, Rana AK (2017) Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design. Superlattice Microst 110:68–81

  22. 22.

    Dubey S, Kondekar PN (2016) Fin shape dependent variability for strained SOI FinFETs. Microelectron Eng 162:63–68

  23. 23.

    TACD Sentaurus process user guide, version I-2013.12, Synopsys Co Mountain view, CA

  24. 24.

    TCAD Sentaurus Device User Guide (2013) Synopsys Inc., mountain view , CA, USA

  25. 25.

    Lanyon HPD, Tuft RA (1978) Bandgap narrowing in heavily doped silicon,” 1978 International Electron Devices Meeting, Washigton, pp. 316–319

  26. 26.

    Masetti G, Severi M, Solmi S (July 1983) Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon. IEEE Trans Electron Devices 30(7):764–769.

  27. 27.

    Ancona MG, Tiersten HF (1987) Macroscopic physics of the silicon inversion layer. Phys Rev B 35(15):7959–7965

  28. 28.

    Venkataraman V, Nawal S, Kumar MJ (2007) Compact analytical threshold-voltage model of nanoscale fully depleted strained-Si on silicon–germanium-on-Insu lator (SGOI) MOSFETs. IEEE Trans Electron Devices 54(3):554–562

Download references


The authors acknowledge the funding by Council of Scientific and Industrial Research, Govt. of India (CSIR Sanction Reference. No. 22(0737)/17/EMR-II).

Author information

Correspondence to Rajesh Saha.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Saha, R., Bhowmick, B. & Baishya, S. Impact of Mole Fractions due to Work Function Variability (WFV) of Metal Gate on Electrical Parameters in Strained SOI-FinFET. Silicon 12, 577–583 (2020).

Download citation


  • Grain orientation
  • Metal gate granularity
  • Mole fraction
  • Strained SOI-FinFET
  • Work function variability