Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential

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One of the basic components of smart power integrated circuits (SPICs) is the laterally diffused metal oxide semiconductor (LDMOS) transistors. In this paper, we propose Fin-LDMOS transistor based on the surface potential. In order to improve the accuracy, we have taken into account not only the fin-shape structure of the gate but also the mobility reduction and saturation velocity. The proposed method is evaluated considering a broad range of biases and physical parameters of the device. The comparison between modeling results and 3D simulations confirm the remarkable accuracy of our model.

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  1. 1.

    Wei J, Luo X, Ma D, Wu J, Li Z, Zhang B (2016) Accumulation mode triple gate SOT LDMOS with ultralow on-resistance and enhanced transconductance. Proceedings of the 28th international symposium on power semiconductor devices and ICs (ISPSD)

  2. 2.

    Cheng S, Fang D, Qiao M, Zhang S, Zhang G, Gu Y, He Y, Zhou X, Qi Z, Li Z, Zhang B, Novel A (2017) 700V deep trench isolated double RESURF LDMOS with P-sink layer. Proceedings of the 29th international symposium on power semiconductor devices & ICs

  3. 3.

    Qiao M, Wang Z, Wang Y, Yu L, Xiao Q, Li Z, Zhang B (2017) 3-D edge termination design and RON,sp-BV model of A 700-V triple RESURF LDMOS with N-type top layer. IEEE Trans Electron Devices 64(6):2579–2586

  4. 4.

    Ge W, Luo X, Wu J, Lv M, Wei J, Ma D, Deng G, Cui W, Yang Y, Zhu K (2017) Ultra-low on-resistance LDMOS with multi-plane electron accumulation layers. IEEE Electron Device Lett 38(7):910–913

  5. 5.

    Saremi M, Ebrahimi B, Afzali-Kusha A, Mohammadi S (2011) A partial-SOI LDMOSFET with triangle buried-oxide for breakdown voltage improvement. Microelectron Reliab 51(12):2069–2076

  6. 6.

    Saremi M, Saremi M, Niazi H, Saremi M, Goharrizi AY (2017) SOI LDMOSFET with up and down extended stepped drift region. J Electron Mater 46(10):5570–5576

  7. 7.

    Pak A, Orouji AA (2016) A novel laminated gate to improve the ON-state resistance of LDMOS transistors. J Comput Electron 15:1071–1076

  8. 8.

    Yi B, Chen X (2017) A 300-V ultra-low-specific on-resistance high-side p-LDMOS with auto-biased n-LDMOS for SPIC. IEEE Trans Power Electron 32(1):551–560

  9. 9.

    Deng G, Wei J, Liu J, Luo X (2016) An ultralow on-resistance high-voltage SOI p-channel LDMOS. Superlattice Microst 100:1029–1041

  10. 10.

    Orouji AA, Pak A (2015) A novel technique for electric field control to improve breakdown voltage. Mater Sci Semicond Process 34:230–235

  11. 11.

    Erlbacher T (2014) Lateral power transistors in integrated circuits. Springer, Cham

  12. 12.

    Pak A, Orouji AA (2017) A novel high performance LDMOS transistor with high channel density. J Comput Electron 17:217–223

  13. 13.

    Hu S, Luo J, Jiang Y, Cheng K, Chen Y, Jin J, Wang J, Zhou J, Tang F, Zhou X, Gan P (2016) Improving breakdown, conductive, and thermal performances for SOI high voltage LDMOS using a partial compound buried layer. Solid State Electron 117:146–151

  14. 14.

    Yang D, Hu S, Lei J, Huang Y, Yuan Q, Jiang Y, Guo J, Cheng K, Lin Z, Zhou X, Tang F (2017) An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars. Superlattice Microst 112:269–278

  15. 15.

    Kumar BS, Shrivastava M (2018) On the unification of physics of quasi-saturation in LDMOS devices. IEEE Trans Electron Devices 65(1):191–198

  16. 16.

    Kumar BS, Shrivastava M (2018) RF, ESD, HCI, SOA, and self heating concerns in LDMOS devices versus quasi-saturation. IEEE Trans Electron Devices 65(1):199–206

  17. 17.

    Avila ES, Tinoco JC, Lopez AGM, Barranca MAR, Cerdeira A, Raskin JP (2016) Parasitic gate resistance impact on triple-gate FinFET CMOS inverter. IEEE Trans Electron Devices 63(7): 2635–2642

  18. 18.

    Saremi M, Afzali-Kusha A, Mohammadi S (2012) Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits. Microelectron Eng 95:74–82

  19. 19.

    Shi L, Jia K, Sun W (Jan. 2013) A Novel compact high-voltage LDMOS transistor model for circuit simulation. IEEE Trans Electron Devices 60(1):346–353

  20. 20.

    Aarts A, D’Halleweyn N, Langevelde RV (2005) A surface-potential-based high-voltage compact LDMOS transistor model. IEEE Trans Electron Devices 52(5):999–1007

  21. 21.

    Dasgupta A, Agarwal A, Khandelwal S, Chauhan YS (2016) Compact modeling of surface potential, charge, and current in nanoscale transistors under quasi-ballistic regime. IEEE Trans Electron Devices 63(11):4151–4159

  22. 22.

    Tsividis Y (2011) Operation and modeling of the MOS transistord3rd edn. Colin McAndrew, New York

  23. 23.

    Atlas User’s Manual (2012) Device simulation software. Silvaco International

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Correspondence to Ali A. Orouji.

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Pak, A., Orouji, A.A. Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential. Silicon 12, 239–244 (2020).

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  • Fin-LDMOS
  • Modeling
  • Channel current
  • Drift region current
  • Surface potential