, Volume 11, Issue 1, pp 513–519 | Cite as

Modeling and Analysis of a Front High-k gate stack Dual-Material Tri-gate Schottky Barrier Silicon-on-Insulator MOSFET with a Dual-Material Bottom Gate

  • Pritha BanerjeeEmail author
  • Subir Kumar Sarkar
Original Paper


The present work centralizes the analytical modeling of a novel structure namely front high-k gate stack Dual-Material Tri-gate Silicon-on-insulator Schottky barrier MOSFET with a dual material bottom gate along with an emphasis on its response towards the various SCEs. 3-D Poisson’s equation along with proper boundary conditions has been solved considering the popular parabolic potential approximation. Different device features like surface potential, threshold voltage, electric field has been studied. Also the device immunity towards the several Short channel effects like drain-induced barrier lowering, threshold voltage roll-off, hot carrier effects are investigated minutely. The analytical results obtained have been verified using simulation results obtained from ATLAS.


Schottky barrier MOSFET Tri-gate MOSFETs Silicon-on-insulator/nothing (SOI/SON) Short channel effects 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.



Pritha Banerjee thankfully acknowledges the financial support obtained from UGC vide file no. 43-293/2014(SR) dated 29.12.2015.


  1. 1.
    D’Agostino F, Quercia D (2000) Introduction to VLSI design (EECS 467), Short-Channel Effects in MOSFETsGoogle Scholar
  2. 2.
    Saha P, Sarkhel S, Sarkar SK (2017) Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET. J Comput Electron Springer 16(3):648–657CrossRefGoogle Scholar
  3. 3.
    Kumar MJ, Chaudhry A (2004) Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans Elect Devices 51(4):569–574CrossRefGoogle Scholar
  4. 4.
    Banerjee P, Sarkar A, Sarkar SK (2017) Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET. Microelectron J 67:50–56CrossRefGoogle Scholar
  5. 5.
    Cartwright J (2011) Intel enters the third dimension. Nature.
  6. 6.
    Srivastava VM, Singh SP (2012) Analysis and design of Tri-Gate MOSFET with high dielectrics gate. I J. Int Syst Appl 5:16–22Google Scholar
  7. 7.
    Frei J, Johns C, Vazquez A, Xiong W, Cleavelin CR, Schulz T, Chaudhary N, Gebara G, Zaman JR, Gostkowski M, Matthews K, Colinge J-P (2004) Body effect in tri- and pi-gate SOI MOSFETs. IEEE Elect Device Lett 25(12):813–815CrossRefGoogle Scholar
  8. 8.
    Singh A, Khosla M, Raj B (2017) Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM. AEU-Int J Electron C 80:67–72CrossRefGoogle Scholar
  9. 9.
    Kumar M, Haldar S, Gupta M, Gupta RS (2016) Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs. Semicond Sci Technol 31:105013. (10pp)CrossRefGoogle Scholar
  10. 10.
    Choi S-J, Choi Y-K Source and drain junction engineering for enhanced non-volatile memory performance, (InTech) ISBN: 978-953-307-272-2.
  11. 11.
    Ajayan J, Nirmal D, Prajoon P, Charles Pravin J (2017) Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications. Int J Electron Commun (AEU) 79:151–157CrossRefGoogle Scholar
  12. 12.
    Ghanatian H, Hosseini SE (2016) Analytical modeling of subthreshold swing in undoped trigate SOI MOSFETs. J Comput Electron:508–515Google Scholar
  13. 13.
    Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs, vol 36Google Scholar
  14. 14.
    Kumar P, Bhowmick B 2-D analytical modeling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET, J Comput Electron.
  15. 15.
    Mohapatra SK, Pradhan KP, Sahu PK, Pati GS, Kumar MR (2014) The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study. Adv Nat Sci Nanosci Nanotechnol 5:045015. (7pp)CrossRefGoogle Scholar
  16. 16.
    Pradhan K. P., Singh D, Mohapatra SK, Sahu PK Double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET: A proposal and analysis. In: 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)Google Scholar
  17. 17.
    Goel E, Kumar S, Singh K, Singh B, Kumar M, Jit S (2016) 2-D analytical modeling of threshold voltage for graded-channel dual-material double-gate MOSFETs. IEEE Trans Elect Devices 63(3):966–973CrossRefGoogle Scholar
  18. 18.
    Chiang T-K (2012) A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans Elect Devices 59(9):2284–2289CrossRefGoogle Scholar

Copyright information

© Springer Nature B.V. 2018

Authors and Affiliations

  1. 1.Department of Electronics & Telecommunication EngineeringJadavpur UniversityKolkataIndia

Personalised recommendations